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CHIPCTL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CLKCTRL

CLKEN_H01

CLKEN_H23

CLKEN_P01

CLKEN_P23

SRST_REQ_H01

SRST_REQ_H23

SRST_REQ_P01

SRST_REQ_P23

POWER_CTRL

WAKEUP_CTRL

REMAP_CTRL

IWDT_CTRL

CLKCFG0

IWDT_CFG

IWDT_CLKDIV

IWDT_RLD

IWDT_STATUS

INTMASK

STATUS0

STATUS1

CHIP_KEY

CLKCFG1

CLKCFG2

VERSION


CLKCTRL

CLKCTRL Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCEN OSCDETEN OSCSTOP OSCGAIN OSCRFEN OSCXCKEN OSCSTB_SEL OSCSTB RCHEN RCHSTB RCHTRIM RCHPT PLLEN PLL_LOCK

OSCEN : OSC enable
bits : 0 - 0 (1 bit)
access : read-write

OSCDETEN : OSC detect enable
bits : 1 - 1 (1 bit)
access : read-write

OSCSTOP : OSC stop
bits : 2 - 2 (1 bit)
access : read-write

OSCGAIN : OSC gain
bits : 4 - 5 (2 bit)
access : read-write

OSCRFEN : OSC internal resistor enable
bits : 6 - 6 (1 bit)
access : read-write

OSCXCKEN : OSCOUT enable
bits : 7 - 7 (1 bit)
access : read-write

OSCSTB_SEL : OSC stable time select
bits : 8 - 9 (2 bit)
access : read-write

OSCSTB : OSC stable status
bits : 11 - 11 (1 bit)
access : read-only

RCHEN : RCH enable
bits : 12 - 12 (1 bit)
access : read-write

RCHSTB : RCH stable status
bits : 14 - 14 (1 bit)
access : read-only

RCHTRIM : RCH trim value
bits : 16 - 23 (8 bit)
access : read-write

RCHPT : RCH temperature trim value
bits : 24 - 27 (4 bit)
access : read-write

PLLEN : PLL enable
bits : 28 - 28 (1 bit)
access : read-write

PLL_LOCK : PLL lock status
bits : 30 - 30 (1 bit)
access : read-only


CLKEN_H01

CLKEN_H01 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_H01 CLKEN_H01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_EN PB_EN PC_EN PD_EN PE_EN PF_EN

PA_EN : port A clock enable
bits : 0 - 0 (1 bit)
access : read-write

PB_EN : port B clock enable
bits : 1 - 1 (1 bit)
access : read-write

PC_EN : port C clock enable
bits : 2 - 2 (1 bit)
access : read-write

PD_EN : port D clock enable
bits : 3 - 3 (1 bit)
access : read-write

PE_EN : port E clock enable
bits : 4 - 4 (1 bit)
access : read-write

PF_EN : port F clock enable
bits : 5 - 5 (1 bit)
access : read-write


CLKEN_H23

CLKEN_H23 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_H23 CLKEN_H23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COPROC_EN ATOM_EN

COPROC_EN : COPROC clock enable
bits : 0 - 0 (1 bit)
access : read-write

ATOM_EN : ATOM clock enable
bits : 2 - 2 (1 bit)
access : read-write


CLKEN_P01

CLKEN_P01 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_P01 CLKEN_P01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPU_EN ERU_EN DMA_EN UART0_EN UART1_EN UART2_EN I2C_EN SSP0_EN SSP1_EN SSP2_EN SSP3_EN CAN_EN

PPU_EN : PPU clock enable
bits : 2 - 2 (1 bit)
access : read-write

ERU_EN : ERU clock enable
bits : 3 - 3 (1 bit)
access : read-write

DMA_EN : DMA clock enable
bits : 6 - 6 (1 bit)
access : read-write

UART0_EN : UART0 clock enable
bits : 16 - 16 (1 bit)
access : read-write

UART1_EN : UART1 clock enable
bits : 17 - 17 (1 bit)
access : read-write

UART2_EN : UART2 clock enable
bits : 18 - 18 (1 bit)
access : read-write

I2C_EN : I2C clock enable
bits : 23 - 23 (1 bit)
access : read-write

SSP0_EN : SSP0 clock enable
bits : 24 - 24 (1 bit)
access : read-write

SSP1_EN : SSP1 clock enable
bits : 25 - 25 (1 bit)
access : read-write

SSP2_EN : SSP2 clock enable
bits : 26 - 26 (1 bit)
access : read-write

SSP3_EN : SSP3 clock enable
bits : 27 - 27 (1 bit)
access : read-write

CAN_EN : CAN clock enable
bits : 30 - 30 (1 bit)
access : read-write


CLKEN_P23

CLKEN_P23 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKEN_P23 CLKEN_P23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECAP_EN EQEP_EN PWM_GP0_EN PWM_GP1_EN ADC_EN CMPSS_EN TIMER_EN

ECAP_EN : ECAP clock enable
bits : 0 - 0 (1 bit)
access : read-write

EQEP_EN : EQEP clock enable
bits : 2 - 2 (1 bit)
access : read-write

PWM_GP0_EN : PWM group0 clock enable
bits : 4 - 4 (1 bit)
access : read-write

PWM_GP1_EN : PWM group1 clock enable
bits : 5 - 5 (1 bit)
access : read-write

ADC_EN : ADC clock enable
bits : 8 - 8 (1 bit)
access : read-write

CMPSS_EN : CMPSS clock enable
bits : 11 - 11 (1 bit)
access : read-write

TIMER_EN : TIMER clock enable
bits : 15 - 15 (1 bit)
access : read-write


SRST_REQ_H01

SRST_REQ_H01 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_H01 SRST_REQ_H01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_RST PB_RST PC_RST PD_RST PE_RST PF_RST

PA_RST : port A software reset
bits : 0 - 0 (1 bit)
access : read-write

PB_RST : port B software reset
bits : 1 - 1 (1 bit)
access : read-write

PC_RST : port C software reset
bits : 2 - 2 (1 bit)
access : read-write

PD_RST : port D software reset
bits : 3 - 3 (1 bit)
access : read-write

PE_RST : port E software reset
bits : 4 - 4 (1 bit)
access : read-write

PF_RST : port F software reset
bits : 5 - 5 (1 bit)
access : read-write


SRST_REQ_H23

SRST_REQ_H23 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_H23 SRST_REQ_H23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COPROC_RST ATOM_RST

COPROC_RST : COPROC software reset
bits : 0 - 0 (1 bit)
access : read-write

ATOM_RST : ATOM software reset
bits : 2 - 2 (1 bit)
access : read-write


SRST_REQ_P01

SRST_REQ_P01 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_P01 SRST_REQ_P01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPU_RST ERU_RST DMA_RST UART0_RST UART1_RST UART2_RST I2C_RST SSP0_RST SSP1_RST SSP2_RST SSP3_RST CAN_RST

PPU_RST : PPU software reset
bits : 2 - 2 (1 bit)
access : read-write

ERU_RST : ERU software reset
bits : 3 - 3 (1 bit)
access : read-write

DMA_RST : DMA software reset
bits : 6 - 6 (1 bit)
access : read-write

UART0_RST : UART0 software reset
bits : 16 - 16 (1 bit)
access : read-write

UART1_RST : UART1 software reset
bits : 17 - 17 (1 bit)
access : read-write

UART2_RST : UART2 software reset
bits : 18 - 18 (1 bit)
access : read-write

I2C_RST : I2C software reset
bits : 23 - 23 (1 bit)
access : read-write

SSP0_RST : SSP0 software reset
bits : 24 - 24 (1 bit)
access : read-write

SSP1_RST : SSP1 software reset
bits : 25 - 25 (1 bit)
access : read-write

SSP2_RST : SSP2 software reset
bits : 26 - 26 (1 bit)
access : read-write

SSP3_RST : SSP3 software reset
bits : 27 - 27 (1 bit)
access : read-write

CAN_RST : CAN software reset
bits : 30 - 30 (1 bit)
access : read-write


SRST_REQ_P23

SRST_REQ_P23 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRST_REQ_P23 SRST_REQ_P23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECAP_RST EQEP_RST PWM_GP0_RST PWM_GP1_RST ADC_RST CMPSS_RST TIMER_RST

ECAP_RST : ECAP software reset
bits : 0 - 0 (1 bit)
access : read-write

EQEP_RST : EQEP software reset
bits : 2 - 2 (1 bit)
access : read-write

PWM_GP0_RST : PWM group0 software reset
bits : 4 - 4 (1 bit)
access : read-write

PWM_GP1_RST : PWM group1 software reset
bits : 5 - 5 (1 bit)
access : read-write

ADC_RST : ADC software reset
bits : 8 - 8 (1 bit)
access : read-write

CMPSS_RST : CMPSS software reset
bits : 11 - 11 (1 bit)
access : read-write

TIMER_RST : TIMER software reset
bits : 15 - 15 (1 bit)
access : read-write


POWER_CTRL

POWER_CTRL Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER_CTRL POWER_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPE SYSCLK_MUX_RSTEN SYSCLK_DETEN DEBUG_NOSLEEP FLASH_CFG FLASH_LPE SRAM_CFG POCREN CVMREN LOCKUPREN MVREN MVRPS MVRSEL LVREN LVRS CVMEN LVDEN LVES LVLS VTSEN VTSEL

LPE : Low Power Enable in deepsleep mode
bits : 0 - 0 (1 bit)
access : read-write

SYSCLK_MUX_RSTEN : system clock select error reset enable
bits : 1 - 1 (1 bit)
access : read-write

SYSCLK_DETEN : system clock detect enable
bits : 2 - 2 (1 bit)
access : read-write

DEBUG_NOSLEEP : low power mode disable in debug mode
bits : 3 - 3 (1 bit)
access : read-write

FLASH_CFG : FLASH clock config in sleep mode
bits : 4 - 4 (1 bit)
access : read-write

FLASH_LPE : FLASH low power enable in deepsleep mode
bits : 5 - 5 (1 bit)
access : read-write

SRAM_CFG : SRAM clock config in sleep mode
bits : 6 - 6 (1 bit)
access : read-write

POCREN : POC reset enable
bits : 8 - 8 (1 bit)
access : read-write

CVMREN : CVM reset enable
bits : 9 - 9 (1 bit)
access : read-write

LOCKUPREN : LOCKUP reset enable
bits : 10 - 10 (1 bit)
access : read-write

MVREN : MVR enable
bits : 11 - 11 (1 bit)
access : read-write

MVRPS : MVR power select
bits : 12 - 12 (1 bit)
access : read-write

MVRSEL : MVR voltage select
bits : 13 - 13 (1 bit)
access : read-write

LVREN : Low Voltage reset enable
bits : 15 - 15 (1 bit)
access : read-write

LVRS : LV reset voltage select
bits : 16 - 17 (2 bit)
access : read-write

CVMEN : CVM enable
bits : 19 - 19 (1 bit)
access : read-write

LVDEN : LVD enable
bits : 20 - 20 (1 bit)
access : read-write

LVES : LV external voltage select
bits : 21 - 21 (1 bit)
access : read-write

LVLS : LV voltage level select
bits : 22 - 24 (3 bit)
access : read-write

VTSEN : VTS enable
bits : 27 - 27 (1 bit)
access : read-write

VTSEL : VTS select
bits : 28 - 29 (2 bit)
access : read-write


WAKEUP_CTRL

WAKEUP_CTRL Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUP_CTRL WAKEUP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO_WAKEUPEN IWDT_WAKEUPEN DEBUG_WAKEUPEN LVD_WAKEUPEN

IO_WAKEUPEN : GPIO wake up enable
bits : 0 - 0 (1 bit)
access : read-write

IWDT_WAKEUPEN : IWDT wake up enable
bits : 2 - 2 (1 bit)
access : read-write

DEBUG_WAKEUPEN : DEBUG wake up enable
bits : 4 - 4 (1 bit)
access : read-write

LVD_WAKEUPEN : LVD wake up enable
bits : 8 - 8 (1 bit)
access : read-write


REMAP_CTRL

REMAP_CTRL Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REMAP_CTRL REMAP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP XRST_USEASFUNC SYSRST_OUTEN SYSRST_SEL DBG_USEASFUNC REMAP_KEY

REMAP : eflash bootloader remap
bits : 0 - 0 (1 bit)
access : read-write

XRST_USEASFUNC : XRST pin used as GPIO
bits : 8 - 8 (1 bit)
access : read-write

SYSRST_OUTEN : system reset output enable
bits : 9 - 9 (1 bit)
access : read-write

SYSRST_SEL : system reset output select
bits : 10 - 10 (1 bit)
access : read-write

DBG_USEASFUNC : DEBUG pin used as GPIO
bits : 12 - 12 (1 bit)
access : read-write

REMAP_KEY : REMAP access enable
bits : 16 - 31 (16 bit)
access : write-only


IWDT_CTRL

IWDT_CTRL Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IWDT_CTRL IWDT_CTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLKCFG0

CLKCFG0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG0 CLKCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC PLLDIV PLLMULT XCLKINSEL XCLKSEL XCLKDIV

PLLSRC : PLL source
bits : 0 - 0 (1 bit)
access : read-write

PLLDIV : PLL reference clock prescale
bits : 4 - 7 (4 bit)
access : read-write

PLLMULT : PLL mult select
bits : 10 - 11 (2 bit)
access : read-write

XCLKINSEL : XCLK input select
bits : 20 - 21 (2 bit)
access : read-write

XCLKSEL : XCLK output select
bits : 24 - 27 (4 bit)
access : read-write

XCLKDIV : XCLK output prescale
bits : 28 - 30 (3 bit)
access : read-write


IWDT_CFG

IWDT_CFG Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_CFG IWDT_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINEN WINSEL

WINEN : window function enable
bits : 0 - 0 (1 bit)
access : read-write

WINSEL : window value select
bits : 8 - 8 (1 bit)
access : read-write


IWDT_CLKDIV

IWDT_CLKDIV Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_CLKDIV IWDT_CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV

CLKDIV : IWDT clock prescale
bits : 0 - 3 (4 bit)
access : read-write


IWDT_RLD

IWDT_RLD Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWDT_RLD IWDT_RLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLD

RLD : IWDT reload value
bits : 0 - 15 (16 bit)
access : read-write


IWDT_STATUS

IWDT_STATUS Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IWDT_STATUS IWDT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT WIN_INTR UPDATING

CNT : IWDT counter
bits : 0 - 15 (16 bit)
access : read-only

WIN_INTR : window mode interrupt status
bits : 16 - 16 (1 bit)
access : read-only

UPDATING : IWDT counter updating
bits : 31 - 31 (1 bit)
access : read-only


INTMASK

INTMASK Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTMASK INTMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR POC CVM LVR LVD NRST WDTRST IWDTRST SRST LOCKUP SYSCLKMUX_RST IO_WAKEUP DBG_WAKEUP RCH_MISS OSC_MISS PLL_MISS SYSCLKMUX_ERR SCLKSEL_CFGERR PLLSRC_CFGERR RCHEN_CFGERR OSCEN_CFGERR PLLEN_CFGERR

POR : POR interrupt mask
bits : 0 - 0 (1 bit)
access : read-write

POC : POC interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

CVM : CVM interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

LVR : LVR interrupt mask
bits : 3 - 3 (1 bit)
access : read-write

LVD : LVD interrupt mask
bits : 4 - 4 (1 bit)
access : read-write

NRST : NRST interrupt mask
bits : 5 - 5 (1 bit)
access : read-write

WDTRST : WDTRST interrupt mask
bits : 6 - 6 (1 bit)
access : read-write

IWDTRST : IWDTRST interrupt mask
bits : 7 - 7 (1 bit)
access : read-write

SRST : SRST interrupt mask
bits : 8 - 8 (1 bit)
access : read-write

LOCKUP : LOCKUP interrupt mask
bits : 9 - 9 (1 bit)
access : read-write

SYSCLKMUX_RST : SYSCLKMUX_RST interrupt mask
bits : 10 - 10 (1 bit)
access : read-write

IO_WAKEUP : IO_WAKEUP interrupt mask
bits : 11 - 11 (1 bit)
access : read-write

DBG_WAKEUP : DBG_WAKEUP interrupt mask
bits : 12 - 12 (1 bit)
access : read-write

RCH_MISS : RCH miss interrupt mask
bits : 16 - 16 (1 bit)
access : read-write

OSC_MISS : OSC miss interrupt mask
bits : 18 - 18 (1 bit)
access : read-write

PLL_MISS : PLL miss interrupt mask
bits : 20 - 20 (1 bit)
access : read-write

SYSCLKMUX_ERR : system clock error interrupt mask
bits : 22 - 22 (1 bit)
access : read-write

SCLKSEL_CFGERR : system clock select config error interrupt mask
bits : 24 - 24 (1 bit)
access : read-write

PLLSRC_CFGERR : PLL source config error interrupt mask
bits : 25 - 25 (1 bit)
access : read-write

RCHEN_CFGERR : RCH enable config error interrupt mask
bits : 27 - 27 (1 bit)
access : read-write

OSCEN_CFGERR : OSC enable config error interrupt mask
bits : 28 - 28 (1 bit)
access : read-write

PLLEN_CFGERR : PLL enable config error interrupt mask
bits : 29 - 29 (1 bit)
access : read-write


STATUS0

STATUS0 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS0 STATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR POC CVM LVR LVD NRST WDTRST IWDTRST SRST LOCKUP SYSCLKMUX_RST IO_WAKEUP DBG_VALID WDT1RST SRST1 LOCKUP1 RCH_MISS OSC_MISS PLL_MISS SYSCLKMUX_ERR SCLKSEL_CFGERR PLLSRC_CFGERR RCHEN_CFGERR OSCEN_CFGERR PLLEN_CFGERR

POR : POR event status
bits : 0 - 0 (1 bit)
access : read-only

POC : POC event status
bits : 1 - 1 (1 bit)
access : read-only

CVM : CVM event status
bits : 2 - 2 (1 bit)
access : read-only

LVR : LVR event status
bits : 3 - 3 (1 bit)
access : read-only

LVD : LVD event status
bits : 4 - 4 (1 bit)
access : read-only

NRST : External Reset event status
bits : 5 - 5 (1 bit)
access : read-only

WDTRST : WDT0 Reset event status
bits : 6 - 6 (1 bit)
access : read-only

IWDTRST : IWDT Reset event status
bits : 7 - 7 (1 bit)
access : read-only

SRST : System Reset event status
bits : 8 - 8 (1 bit)
access : read-only

LOCKUP : LOCKUP event status
bits : 9 - 9 (1 bit)
access : read-only

SYSCLKMUX_RST : SYSCLKMUX_RST event status
bits : 10 - 10 (1 bit)
access : read-only

IO_WAKEUP : IO_WAKEUP event status
bits : 11 - 11 (1 bit)
access : read-only

DBG_VALID : DBG VALID event status
bits : 12 - 12 (1 bit)
access : read-only

WDT1RST : WDT1RST event status
bits : 13 - 13 (1 bit)
access : read-only

SRST1 : Core 1 System Reset event status
bits : 14 - 14 (1 bit)
access : read-only

LOCKUP1 : Core 1 LOCKUP event status
bits : 15 - 15 (1 bit)
access : read-only

RCH_MISS : RCH miss event status
bits : 16 - 16 (1 bit)
access : read-only

OSC_MISS : OSC miss event status
bits : 18 - 18 (1 bit)
access : read-only

PLL_MISS : PLL miss event status
bits : 20 - 20 (1 bit)
access : read-only

SYSCLKMUX_ERR : system clock error event status
bits : 22 - 22 (1 bit)
access : read-only

SCLKSEL_CFGERR : system clock select config error event status
bits : 24 - 24 (1 bit)
access : read-only

PLLSRC_CFGERR : PLL source config error event status
bits : 25 - 25 (1 bit)
access : read-only

RCHEN_CFGERR : RCH enable config error event status
bits : 27 - 27 (1 bit)
access : read-only

OSCEN_CFGERR : OSC enable config error event status
bits : 28 - 28 (1 bit)
access : read-only

PLLEN_CFGERR : PLL enable config error event status
bits : 29 - 29 (1 bit)
access : read-only


STATUS1

STATUS1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS1 STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCSTOP RCHSTB PLLLOCK LVDFLAG CVMFLAG BGRFLAG IWDT_INTR

OSCSTOP : OSC stop status
bits : 0 - 0 (1 bit)
access : read-only

RCHSTB : RCH stable status
bits : 3 - 3 (1 bit)
access : read-only

PLLLOCK : PLL lock status
bits : 5 - 5 (1 bit)
access : read-only

LVDFLAG : LVD flag
bits : 7 - 7 (1 bit)
access : read-only

CVMFLAG : CVM flag
bits : 9 - 9 (1 bit)
access : read-only

BGRFLAG : BGR flag
bits : 11 - 11 (1 bit)
access : read-only

IWDT_INTR : IWDT interrupt status
bits : 13 - 13 (1 bit)
access : read-only


CHIP_KEY

CHIP_KEY Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_KEY CHIP_KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLKCFG1

CLKCFG1 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG1 CLKCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCLKSEL SYSCLKLOCK SYSTICKSEL

SYSCLKSEL : system clock select
bits : 0 - 1 (2 bit)
access : read-write

SYSCLKLOCK : system clock lock status
bits : 4 - 4 (1 bit)
access : read-only

SYSTICKSEL : systick clock select
bits : 8 - 9 (2 bit)
access : read-write


CLKCFG2

CLKCFG2 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCFG2 CLKCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDIV MTDIV PDIV01 PDIV23

HDIV : AHB clock prescale
bits : 0 - 7 (8 bit)
access : read-write

MTDIV : motor control clock prescale
bits : 8 - 11 (4 bit)
access : read-write

PDIV01 : APB01 clock prescale
bits : 16 - 19 (4 bit)
access : read-write

PDIV23 : APB23 clock prescale
bits : 24 - 27 (4 bit)
access : read-write


VERSION

VERSION Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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