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ERU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

ERUINSEL

ERUINCTRL0

ERUINCTRL1

ERUINCTRL2

ERUINCTRL3

ERUOUTCTRL0

ERUOUTCTRL1

ERUOUTCTRL2

ERUOUTCTRL3


ERUINSEL

ERU Input Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERUINSEL ERUINSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 in0_sela in0_selb in1_sela in1_selb in2_sela in2_selb in3_sela in3_selb

in0_sela : A0 Event Source Select
bits : 0 - 2 (3 bit)
access : read-write

in0_selb : B0 Event Source Select
bits : 4 - 6 (3 bit)
access : read-write

in1_sela : A1 Event Source Select
bits : 8 - 10 (3 bit)
access : read-write

in1_selb : B1 Event Source Select
bits : 12 - 14 (3 bit)
access : read-write

in2_sela : A2 Event Source Select
bits : 16 - 18 (3 bit)
access : read-write

in2_selb : B2 Event Source Select
bits : 20 - 22 (3 bit)
access : read-write

in3_sela : A3 Event Source Select
bits : 24 - 26 (3 bit)
access : read-write

in3_selb : B3 Event Source Select
bits : 28 - 30 (3 bit)
access : read-write


ERUINCTRL0

ERU Input Control Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERUINCTRL0 ERUINCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPE LVL_DET RE FE OCS FL ERSOSEL APOL BPOL

OTPE : ETL0 Output Trigger Pulse Enable
bits : 0 - 0 (1 bit)
access : read-write

LVL_DET : ETL0 Reconstruction of the Status Flag Level Detection
bits : 1 - 1 (1 bit)
access : read-write

RE : ETL0 Rising Edge Test Enable
bits : 2 - 2 (1 bit)
access : read-write

FE : ETL0 Falling Edge Test Enable
bits : 3 - 3 (1 bit)
access : read-write

OCS : ETL0 Output Trigger Pulse Output Channel Choice
bits : 4 - 6 (3 bit)
access : read-write

FL : ETL0 status flag
bits : 8 - 8 (1 bit)
access : read-write

ERSOSEL : ERS0 input source Selecet
bits : 16 - 17 (2 bit)
access : read-write

APOL : The polarity of the input A choice
bits : 18 - 18 (1 bit)
access : read-write

BPOL : The polarity of the input B choice
bits : 19 - 19 (1 bit)
access : read-write


ERUINCTRL1


address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUINCTRL1 ERUINCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERUINCTRL2


address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUINCTRL2 ERUINCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERUINCTRL3


address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUINCTRL3 ERUINCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERUOUTCTRL0

ERU Output Control Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERUOUTCTRL0 ERUOUTCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISS GEEN PDR GP IPEN0 IPEN1 IPEN2 IPEN3

ISS : Internal trigger source choice
bits : 0 - 1 (2 bit)
access : read-write

GEEN : Door control events enable
bits : 2 - 2 (1 bit)
access : read-write

PDR : Model test results flag
bits : 3 - 3 (1 bit)
access : read-only

GP : Model test results of gating options
bits : 4 - 5 (2 bit)
access : read-write

IPEN0 : ETL0 Model test enable
bits : 16 - 16 (1 bit)
access : read-write

IPEN1 : ETL1 Model test enable
bits : 17 - 17 (1 bit)
access : read-write

IPEN2 : ETL2 Model test enable
bits : 18 - 18 (1 bit)
access : read-write

IPEN3 : ETL3 Model test enable
bits : 19 - 19 (1 bit)
access : read-write


ERUOUTCTRL1


address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUOUTCTRL1 ERUOUTCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERUOUTCTRL2


address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUOUTCTRL2 ERUOUTCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ERUOUTCTRL3


address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0

ERUOUTCTRL3 ERUOUTCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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