\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
DMA Configure Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA ENABLE
bits : 0 - 0 (1 bit)
access : read-write
PORT : DMA PORT
bits : 1 - 3 (3 bit)
access : read-write
RESET : DMA RESET
bits : 31 - 31 (1 bit)
access : read-write
DMA Channel 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
DMA Channel 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
DMA Channel 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
DMA Channel 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
DMA Channel 4 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
DMA Channel 5 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write
CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write
CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write
CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write
CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write
CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write
CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write
CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write
CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write
CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write
CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write
Channel Control Base Address Pointer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Channel Standby Control Base Address Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Software Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMA Status Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Package Size
bits : 0 - 0 (1 bit)
access : read-only
STATE : Transmit Size
bits : 4 - 7 (4 bit)
access : read-only
CREQ_NUM_MINUS1 : Busy
bits : 8 - 12 (5 bit)
access : read-only
CHNL_NUM_MINUS1 : Busy
bits : 16 - 20 (5 bit)
access : read-only
DMA Version Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA Request Wait Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Active Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Done Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Configure Error Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bus Error Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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