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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CFG

CTRL0

CTRL1

CTRL2

CTRL3

CTRL4

CTRL5

BASE_PTR

ALT_BASE_PTR

SW_REQ

STATUS

VERSION

REQUEST_ON

ACTIVE

DONE

CFG_ERR

BUS_ERR


CFG

DMA Configure Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE PORT RESET

ENABLE : DMA ENABLE
bits : 0 - 0 (1 bit)
access : read-write

PORT : DMA PORT
bits : 1 - 3 (3 bit)
access : read-write

RESET : DMA RESET
bits : 31 - 31 (1 bit)
access : read-write


CTRL0

DMA Channel 0 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


CTRL1

DMA Channel 1 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


CTRL2

DMA Channel 2 Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


CTRL3

DMA Channel 3 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


CTRL4

DMA Channel 4 Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL4 CTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


CTRL5

DMA Channel 5 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL5 CTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_ENABLE CHNL_PRI_ALT CHNL_USE_BURST CHNL_PRIORITY CHNL_REQ0_SEL CHNL_REQ0_MASK CHNL_REQ1_SEL CHNL_REQ1_MASK CHNL_BUSERR_INTREN CHNL_CFGERR_INTREN CHNL_DMADONE_INTREN

CHNL_ENABLE : Channel n enable
bits : 0 - 0 (1 bit)
access : read-write

CHNL_PRI_ALT : Select the pointer of the main / standby base of n channel
bits : 2 - 2 (1 bit)
access : read-write

CHNL_USE_BURST : Channel n uses continuous transmission
bits : 4 - 4 (1 bit)
access : read-write

CHNL_PRIORITY : priority setting of Channel n
bits : 5 - 5 (1 bit)
access : read-write

CHNL_REQ0_SEL : Channel n request option 0
bits : 8 - 12 (5 bit)
access : read-write

CHNL_REQ0_MASK : Channel n request 0 shielding
bits : 15 - 15 (1 bit)
access : read-write

CHNL_REQ1_SEL : Channel n request option 1
bits : 16 - 20 (5 bit)
access : read-write

CHNL_REQ1_MASK : Channel n request 1 shielding
bits : 23 - 23 (1 bit)
access : read-write

CHNL_BUSERR_INTREN : bus error interrupt enable of channel n
bits : 24 - 24 (1 bit)
access : read-write

CHNL_CFGERR_INTREN : configuration error interrupt enable of channel n
bits : 25 - 25 (1 bit)
access : read-write

CHNL_DMADONE_INTREN : DMA completes the interrupt enable of channel n
bits : 28 - 28 (1 bit)
access : read-write


BASE_PTR

Channel Control Base Address Pointer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_PTR BASE_PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ALT_BASE_PTR

Channel Standby Control Base Address Pointer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALT_BASE_PTR ALT_BASE_PTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SW_REQ

Software Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SW_REQ SW_REQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STATUS

DMA Status Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE STATE CREQ_NUM_MINUS1 CHNL_NUM_MINUS1

ENABLE : Package Size
bits : 0 - 0 (1 bit)
access : read-only

STATE : Transmit Size
bits : 4 - 7 (4 bit)
access : read-only

CREQ_NUM_MINUS1 : Busy
bits : 8 - 12 (5 bit)
access : read-only

CHNL_NUM_MINUS1 : Busy
bits : 16 - 20 (5 bit)
access : read-only


VERSION

DMA Version Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

REQUEST_ON

DMA Request Wait Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REQUEST_ON REQUEST_ON read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ACTIVE

Active Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACTIVE ACTIVE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DONE

Done Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DONE DONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFG_ERR

Configure Error Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG_ERR CFG_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUS_ERR

Bus Error Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUS_ERR BUS_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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