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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

CSET

DATA

SR

MEXT

SEXT

TOUT

CCLR

CSR

ADDR


CSET

I2C Control Set Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CSET CSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR0 CR1 AA STO STA EN CR2 CR3

CR0 : CR0
bits : 0 - 0 (1 bit)
access : write-only

CR1 : CR1
bits : 1 - 1 (1 bit)
access : write-only

AA : ACK bit
bits : 2 - 2 (1 bit)
access : write-only

STO : Send Stop Bit
bits : 4 - 4 (1 bit)
access : write-only

STA : Send Start Bit
bits : 5 - 5 (1 bit)
access : write-only

EN : Enable
bits : 6 - 6 (1 bit)
access : write-only

CR2 : CR2
bits : 7 - 7 (1 bit)
access : write-only

CR3 : CR3
bits : 9 - 9 (1 bit)
access : write-only


DATA

I2C Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : I2C Data Register
bits : 0 - 7 (8 bit)
access : read-write


SR

I2C Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STAT

STAT : I2C Status
bits : 0 - 7 (8 bit)
access : read-only


MEXT

TMEX timeout detection Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEXT MEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEXT

MEXT : TMEX timeout detection Register
bits : 0 - 7 (8 bit)
access : read-write


SEXT

SEXT timeout detection Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEXT SEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEXT

SEXT : SEXT timeout detection Register
bits : 0 - 7 (8 bit)
access : read-write


TOUT

timeout detection Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOUT TOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUT

TOUT : timeout detection Register
bits : 0 - 7 (8 bit)
access : read-write


CCLR

I2C Control Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CCLR CCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR0 CR1 AA SI STO STA EN CR2 CR3

CR0 : CR0
bits : 0 - 0 (1 bit)
access : write-only

CR1 : CR1
bits : 1 - 1 (1 bit)
access : write-only

AA : ACK bit
bits : 2 - 2 (1 bit)
access : write-only

SI : Clear Interrupt bit
bits : 3 - 3 (1 bit)
access : write-only

STO : Send Stop Bit
bits : 4 - 4 (1 bit)
access : write-only

STA : Send Start Bit
bits : 5 - 5 (1 bit)
access : write-only

EN : Enable
bits : 6 - 6 (1 bit)
access : write-only

CR2 : CR2
bits : 7 - 7 (1 bit)
access : write-only

CR3 : CR3
bits : 9 - 9 (1 bit)
access : write-only


CSR

I2C Control Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR0 CR1 AA SI STO STA EN CR2 CR3

CR0 : CR0
bits : 0 - 0 (1 bit)
access : read-only

CR1 : CR1
bits : 1 - 1 (1 bit)
access : read-only

AA : ACK bit
bits : 2 - 2 (1 bit)
access : read-only

SI : Clear Interrupt bit
bits : 3 - 3 (1 bit)
access : read-only

STO : Send Stop Bit
bits : 4 - 4 (1 bit)
access : read-only

STA : Send Start Bit
bits : 5 - 5 (1 bit)
access : read-only

EN : Enable
bits : 6 - 6 (1 bit)
access : read-only

CR2 : CR2
bits : 7 - 7 (1 bit)
access : read-only

CR3 : CR3
bits : 9 - 9 (1 bit)
access : read-only


ADDR

I2C Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC ADDR

GC : Broadcast Ack Signal
bits : 0 - 0 (1 bit)
access : read-write

ADDR : Address
bits : 1 - 7 (7 bit)
access : read-write



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