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SSP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

SSPCR0

SSPCPSR

SSPIMSC

SSPRIS

SSPMIS

SSPICR

SSPDMACR

SSPCR1

SSPDR

SSPSR

SSPPID0

SSPPID1

SSPPID2

SSPPID3

SSPPCID0

SSPPCID1

SSPPCID2

SSPPCID3


SSPCR0

Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCR0 SSPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSS FRF SPO SPH SCR

DSS : Data Size Select
bits : 0 - 3 (4 bit)
access : read-write

FRF : Frame format
bits : 4 - 5 (2 bit)
access : read-write

SPO : SSPCLKOUT polarity
bits : 6 - 6 (1 bit)
access : read-write

SPH : SSPCLKOUT phase
bits : 7 - 7 (1 bit)
access : read-write

SCR : Serial Clock rate
bits : 8 - 15 (8 bit)
access : read-write


SSPCPSR

Clock prescale Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCPSR SSPCPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSDVSR

CPSDVSR : Clock prescale divisor
bits : 0 - 7 (8 bit)
access : read-write


SSPIMSC

Interrupt Set or Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPIMSC SSPIMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIM RTIM RXIM TXIM

RORIM : Receive overrun interrupt mask
bits : 0 - 0 (1 bit)
access : read-write

RTIM : Receive timeout interrupt mask
bits : 1 - 1 (1 bit)
access : read-write

RXIM : Receive FIFO interrupt mask
bits : 2 - 2 (1 bit)
access : read-write

TXIM : Receive FIFO interrupt mask
bits : 3 - 3 (1 bit)
access : read-write


SSPRIS

Raw Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPRIS SSPRIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORRIS RTRIS RXRIS TXRIS

RORRIS : Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only

RTRIS : Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXRIS : Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only

TXRIS : Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only


SSPMIS

Masked Interrupt Staus Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPMIS SSPMIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORMIS RTMIS RXMIS TXMIS

RORMIS : Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : read-only

RTMIS : Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXMIS : Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
bits : 2 - 2 (1 bit)
access : read-only

TXMIS : Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
bits : 3 - 3 (1 bit)
access : read-only


SSPICR

Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SSPICR SSPICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIC RTIC

RORIC : Clears the SSPRORINTR interrupt
bits : 0 - 0 (1 bit)
access : write-only

RTIC : Clears the SSPRTINTR interrupt
bits : 1 - 1 (1 bit)
access : write-only


SSPDMACR

DMA Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPDMACR SSPDMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE

RXDMAE : Receive DMA Enable.
bits : 0 - 0 (1 bit)
access : read-write

TXDMAE : Transmit DMA Enable
bits : 1 - 1 (1 bit)
access : read-write


SSPCR1

Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPCR1 SSPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM SSE MS SOD DMALEV

LBM : Loop back mode
bits : 0 - 0 (1 bit)
access : read-write

SSE : Synchronous serial port enable
bits : 1 - 1 (1 bit)
access : read-write

MS : Master or Slave mode select
bits : 2 - 2 (1 bit)
access : read-write

SOD : Clear Data Overrun
bits : 3 - 3 (1 bit)
access : read-write

DMALEV : DMA RX FIFO trig level
bits : 4 - 6 (3 bit)
access : read-write


SSPDR

Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSPDR SSPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Transmit/Receive FIFO
bits : 0 - 15 (16 bit)
access : read-write


SSPSR

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPSR SSPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TNF RNE RFF BSY

TFE : Transmit FIFO emptyt
bits : 0 - 0 (1 bit)
access : read-only

TNF : Transmit FIFO full
bits : 1 - 1 (1 bit)
access : read-only

RNE : Receive FIFO not empty
bits : 2 - 2 (1 bit)
access : read-only

RFF : Receive FIFO full
bits : 3 - 3 (1 bit)
access : read-only

BSY : PrimeCell SSP busy flag
bits : 4 - 4 (1 bit)
access : read-only


SSPPID0

Peripheral Identification Register0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPID0 SSPPID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPID1

Peripheral Identification Register1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPID1 SSPPID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPID2

Peripheral Identification Register2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPID2 SSPPID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPID3

Peripheral Identification Register3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPID3 SSPPID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPCID0

PrimCell Identification Register0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPCID0 SSPPCID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPCID1

PrimCell Identification Register1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPCID1 SSPPCID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPCID2

PrimCell Identification Register2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPCID2 SSPPCID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSPPCID3

PrimCell Identification Register3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPPCID3 SSPPCID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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