\n

CAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

MODE

FI

COD

IER

BTR

EWL

SR

RFS

RID

RDA

RDB

COMMAND

ID

MSK

AFC

AFT

GSR

DA

DMAEN

DMASR

ISR

DB


MODE

CAN Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM LOM STM TPM RPM TM

RM : Reset Mode
bits : 0 - 0 (1 bit)
access : read-write

LOM : Listen Only Mode
bits : 1 - 1 (1 bit)
access : read-write

STM : Self test Mode
bits : 2 - 2 (1 bit)
access : read-write

TPM : Test Priority Mode
bits : 3 - 3 (1 bit)
access : read-write

RPM : Receive Polarity Mode
bits : 5 - 5 (1 bit)
access : read-write

TM : Test Mode
bits : 7 - 7 (1 bit)
access : read-write


FI

CAN Transmit Frame Information Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FI FI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC PRIO

DLC : Transmit Data Length Code
bits : 0 - 3 (4 bit)
access : read-write

PRIO : PRIO
bits : 24 - 31 (8 bit)
access : read-write


COD

CAN Receive Filter Code Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COD COD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IER

CAN Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIE TIE0 EIE DOIE EPIE ALIE BEIE TIE1 TIE2 DFIE

RIE : Receiver Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

TIE0 : Transmit Interrupt Enable for Buffer 0
bits : 1 - 1 (1 bit)
access : read-write

EIE : Error Warning Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

DOIE : Data Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

EPIE : Error Passive Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

ALIE : Arbitration Lost Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BEIE : Bus Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

TIE1 : Transmit Interrupt Enable for Buffer 1
bits : 9 - 9 (1 bit)
access : read-write

TIE2 : Transmit Interrupt Enable for Buffer 2
bits : 10 - 10 (1 bit)
access : read-write

DFIE : Receive FIFO Full Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write


BTR

CAN Bus Timing Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR BTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRP SJW TESG1 TESG2 SAM

BRP : Baud Rate Prescaler
bits : 0 - 9 (10 bit)
access : read-write

SJW : The Synchronization Jump Width is CAN clocks
bits : 14 - 15 (2 bit)
access : read-write

TESG1 : The delay from the nominal Sync point to the sample point is (this value plus one)CAN clocks.
bits : 16 - 19 (4 bit)
access : read-write

TESG2 : The delay from the sample point to the next nominal sync point is (this value plus one)CAN clocks
bits : 20 - 22 (3 bit)
access : read-write

SAM : Sampling
bits : 23 - 23 (1 bit)
access : read-write


EWL

CAN Error Warning Limit Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EWL EWL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SR

CAN Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBS0 DOS0 TBS0 TCS0 RS0 TS0 ES0 BS0 RBS1 DOS1 TBS1 TCS1 RS1 TS1 ES1 BS1 RBS2 DOS2 TBS2 TCS2 RS2 TS2 ES2 BS2

RBS0 : Receive Buffer Status
bits : 0 - 0 (1 bit)
access : read-only

DOS0 : Data Overrun Status
bits : 1 - 1 (1 bit)
access : read-only

TBS0 : Transmit Buffer Status 0
bits : 2 - 2 (1 bit)
access : read-only

TCS0 : Tx Buffer 0 Transmission Complete Status
bits : 3 - 3 (1 bit)
access : read-only

RS0 : Receive Status
bits : 4 - 4 (1 bit)
access : read-only

TS0 : Receive Status 0
bits : 5 - 5 (1 bit)
access : read-only

ES0 : Error Status
bits : 6 - 6 (1 bit)
access : read-only

BS0 : Bus Status
bits : 7 - 7 (1 bit)
access : read-only

RBS1 : Receive Buffer Status
bits : 8 - 8 (1 bit)
access : read-only

DOS1 : Data Overrun Status
bits : 9 - 9 (1 bit)
access : read-only

TBS1 : Transmit Buffer Status 1
bits : 10 - 10 (1 bit)
access : read-only

TCS1 : Tx Buffer1 Transmission Complete Status
bits : 11 - 11 (1 bit)
access : read-only

RS1 : Receive Status
bits : 12 - 12 (1 bit)
access : read-only

TS1 : Receive Status 1
bits : 13 - 13 (1 bit)
access : read-only

ES1 : Error Status
bits : 14 - 14 (1 bit)
access : read-only

BS1 : Bus Status
bits : 15 - 15 (1 bit)
access : read-only

RBS2 : Receive Buffer Status
bits : 16 - 16 (1 bit)
access : read-only

DOS2 : Data Overrun Status
bits : 17 - 17 (1 bit)
access : read-only

TBS2 : Transmit Buffer Status 2
bits : 18 - 18 (1 bit)
access : read-only

TCS2 : Tx Buffer 2 Transmission Complete Status
bits : 19 - 19 (1 bit)
access : read-only

RS2 : Receive Status
bits : 20 - 20 (1 bit)
access : read-only

TS2 : Receive Status 2
bits : 21 - 21 (1 bit)
access : read-only

ES2 : Error Status
bits : 22 - 22 (1 bit)
access : read-only

BS2 : Bus Status
bits : 23 - 23 (1 bit)
access : read-only


RFS

CAN Receive Frame Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFS RFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC ACF0 ACF1 ACF2 ACF3 ACF4 ACF5 ACF6 ACF7 ACF8 ACF9 ACF10 ACF11 ACF12 ACF13

DLC : Data Length Code
bits : 0 - 3 (4 bit)
access : read-only

ACF0 : ACF0
bits : 16 - 16 (1 bit)
access : read-only

ACF1 : ACF1
bits : 17 - 17 (1 bit)
access : read-only

ACF2 : ACF2
bits : 18 - 18 (1 bit)
access : read-only

ACF3 : ACF3
bits : 19 - 19 (1 bit)
access : read-only

ACF4 : ACF4
bits : 20 - 20 (1 bit)
access : read-only

ACF5 : ACF5
bits : 21 - 21 (1 bit)
access : read-only

ACF6 : ACF6
bits : 22 - 22 (1 bit)
access : read-only

ACF7 : ACF7
bits : 24 - 24 (1 bit)
access : read-only

ACF8 : ACF8
bits : 25 - 25 (1 bit)
access : read-only

ACF9 : ACF9
bits : 26 - 26 (1 bit)
access : read-only

ACF10 : ACF10
bits : 27 - 27 (1 bit)
access : read-only

ACF11 : ACF11
bits : 28 - 28 (1 bit)
access : read-only

ACF12 : ACF12
bits : 29 - 29 (1 bit)
access : read-only

ACF13 : ACF13
bits : 30 - 30 (1 bit)
access : read-only


RID

CAN Receive Identification Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RID RID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTR FF ID

RTR : RTR
bits : 1 - 1 (1 bit)
access : read-only

FF : FF
bits : 2 - 2 (1 bit)
access : read-only

ID : ID
bits : 3 - 31 (29 bit)
access : read-only


RDA

CAN Receive Low Byte Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDA RDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : DATA0
bits : 0 - 7 (8 bit)
access : read-only

DATA1 : DATA1
bits : 8 - 15 (8 bit)
access : read-only

DATA2 : DATA2
bits : 16 - 23 (8 bit)
access : read-only

DATA3 : DATA3
bits : 24 - 31 (8 bit)
access : read-only


RDB

CAN Receive High Byte Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDB RDB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : DATA4
bits : 0 - 7 (8 bit)
access : read-only

DATA5 : DATA5
bits : 8 - 15 (8 bit)
access : read-only

DATA6 : DATA6
bits : 16 - 23 (8 bit)
access : read-only

DATA7 : DATA7
bits : 24 - 31 (8 bit)
access : read-only


COMMAND

CAN Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMMAND COMMAND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR AT RRB CDO SRR STB0 STB1 STB2 CAB CBF

TR : Transmisson Request
bits : 0 - 0 (1 bit)
access : read-write

AT : Abort Transmission
bits : 1 - 1 (1 bit)
access : read-write

RRB : Release Receive Buffer
bits : 2 - 2 (1 bit)
access : read-write

CDO : Clear Data Overrun
bits : 3 - 3 (1 bit)
access : read-write

SRR : Self Reception Request
bits : 4 - 4 (1 bit)
access : read-write

STB0 : Select Tx Buffer 0
bits : 5 - 5 (1 bit)
access : read-write

STB1 : Select Tx Buffer 1
bits : 6 - 6 (1 bit)
access : read-write

STB2 : Select Tx Buffer 2
bits : 7 - 7 (1 bit)
access : read-write

CAB : Clear All Buffer
bits : 8 - 8 (1 bit)
access : read-write

CBF : Clear Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-write


ID

CAN Transmit Identification Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTR FF ID

RTR : RTR
bits : 1 - 1 (1 bit)
access : read-write

FF : FF
bits : 2 - 2 (1 bit)
access : read-write

ID : ID
bits : 3 - 31 (29 bit)
access : read-write


MSK

CAN Receive Filter Mask Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSK MSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFC

CAN Transmit Frame Information Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFC AFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFC0EN AFC1EN AFC2EN AFC3EN AFC4EN AFC5EN AFC6EN

AFC0EN : Automatic filter 0 enable
bits : 0 - 0 (1 bit)
access : read-write

AFC1EN : Automatic filter 1 enable
bits : 1 - 1 (1 bit)
access : read-write

AFC2EN : Automatic filter 2 enable
bits : 2 - 2 (1 bit)
access : read-write

AFC3EN : Automatic filter 3 enable
bits : 3 - 3 (1 bit)
access : read-write

AFC4EN : Automatic filter 4 enable
bits : 4 - 4 (1 bit)
access : read-write

AFC5EN : Automatic filter 5 enable
bits : 5 - 5 (1 bit)
access : read-write

AFC6EN : Automatic filter 6 enable
bits : 6 - 6 (1 bit)
access : read-write


AFT

CAN Transmit Identification Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFT AFT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFC0TYPE AFC1TYPE AFC2TYPE AFC3TYPE AFC4TYPE AFC5TYPE AFC6TYPE

AFC0TYPE : Automatic filter 0 type
bits : 0 - 0 (1 bit)
access : read-write

AFC1TYPE : Automatic filter 1 type
bits : 1 - 1 (1 bit)
access : read-write

AFC2TYPE : Automatic filter 2 type
bits : 2 - 2 (1 bit)
access : read-write

AFC3TYPE : Automatic filter 3 type
bits : 3 - 3 (1 bit)
access : read-write

AFC4TYPE : Automatic filter 4 type
bits : 4 - 4 (1 bit)
access : read-write

AFC5TYPE : Automatic filter 5 type
bits : 5 - 5 (1 bit)
access : read-write

AFC6TYPE : Automatic filter 6 type
bits : 6 - 6 (1 bit)
access : read-write


GSR

CAN Global Status and Error Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GSR GSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBS DOS TBS TCS RS TS ES BS RBF TXSEL RXCNT RXERR TXERR

RBS : Receive Buffer Status
bits : 0 - 0 (1 bit)
access : read-only

DOS : Data Overrun Status
bits : 1 - 1 (1 bit)
access : read-only

TBS : Transmit Buffer Status
bits : 2 - 2 (1 bit)
access : read-only

TCS : Transmit Complete Status
bits : 3 - 3 (1 bit)
access : read-only

RS : Receive Status
bits : 4 - 4 (1 bit)
access : read-only

TS : Transmit Status
bits : 5 - 5 (1 bit)
access : read-only

ES : Error Status
bits : 6 - 6 (1 bit)
access : read-only

BS : Bus Status
bits : 7 - 7 (1 bit)
access : read-only

RBF : Receive Buffer Full
bits : 8 - 8 (1 bit)
access : read-only

TXSEL : Tx Buffer Select
bits : 9 - 11 (3 bit)
access : read-only

RXCNT : Rx Buffer Counter
bits : 12 - 15 (4 bit)
access : read-only

RXERR : The current value of the Rx Counter
bits : 16 - 23 (8 bit)
access : read-write

TXERR : The current value of the Tx Counter
bits : 24 - 31 (8 bit)
access : read-write


DA

CAN Transmit Low Byte Register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DA DA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : DATA0
bits : 0 - 7 (8 bit)
access : read-write

DATA1 : DATA1
bits : 8 - 15 (8 bit)
access : read-write

DATA2 : DATA2
bits : 16 - 23 (8 bit)
access : read-write

DATA3 : DATA3
bits : 24 - 31 (8 bit)
access : read-write


DMAEN

CAN DMA Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN DMAEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB0DMAEN RBDMAEN RBSEL AUTORRB TB1DMAEN TB2DMAEN

TB0DMAEN : Transmit Buffer 0 DMA Enable
bits : 0 - 0 (1 bit)
access : read-write

RBDMAEN : Receive Buffer DMA Enable
bits : 1 - 1 (1 bit)
access : read-write

RBSEL : Receive Buffer DMA Trig Level Select
bits : 2 - 3 (2 bit)
access : read-write

AUTORRB : Auto RRB Enable
bits : 4 - 4 (1 bit)
access : read-write

TB1DMAEN : Transmit Buffer 1 DMA Enable
bits : 5 - 5 (1 bit)
access : read-write

TB2DMAEN : Transmit Buffer 2 DMA Enable
bits : 6 - 6 (1 bit)
access : read-write


DMASR

CAN DMA Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMASR DMASR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB0DMASR RBDMASR AUTORRB TB1DMASR TB2DMASR

TB0DMASR : Transmit Buffer 0 DMA Status
bits : 0 - 0 (1 bit)
access : read-only

RBDMASR : Receive Buffer DMA Status
bits : 1 - 1 (1 bit)
access : read-only

AUTORRB : Auto RRB Status
bits : 4 - 4 (1 bit)
access : read-only

TB1DMASR : Transmit Buffer 1 DMA Status
bits : 5 - 5 (1 bit)
access : read-only

TB2DMASR : Transmit Buffer 2 DMA Status
bits : 6 - 6 (1 bit)
access : read-only


ISR

CAN Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RI TI0 EI DOI EPI ALI BEI TI1 TI2 DFI ERRBIT ERRDIR ERRC ALCBIT

RI : Receive Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TI0 : Transmit Interrupt 0
bits : 1 - 1 (1 bit)
access : read-only

EI : Error Warning Interrupt
bits : 2 - 2 (1 bit)
access : read-only

DOI : Data Overrun Interrupt
bits : 3 - 3 (1 bit)
access : read-only

EPI : Error Passive Interrupt
bits : 5 - 5 (1 bit)
access : read-only

ALI : Arbitration Lost Interrupt
bits : 6 - 6 (1 bit)
access : read-only

BEI : Bus Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only

TI1 : Transmit Interrupt 1
bits : 9 - 9 (1 bit)
access : read-only

TI2 : Transmit Interrupt 2
bits : 10 - 10 (1 bit)
access : read-only

DFI : Receive FIFO Full Interrupt
bits : 11 - 11 (1 bit)
access : read-only

ERRBIT : Error Code Capture
bits : 16 - 20 (5 bit)
access : read-only

ERRDIR : Error Direction
bits : 21 - 21 (1 bit)
access : read-only

ERRC : Error Type
bits : 22 - 23 (2 bit)
access : read-only

ALCBIT : Error Type
bits : 24 - 28 (5 bit)
access : read-only


DB

CAN Transmit High Byte Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DB DB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : DATA4
bits : 0 - 7 (8 bit)
access : read-write

DATA5 : DATA5
bits : 8 - 15 (8 bit)
access : read-write

DATA6 : DATA6
bits : 16 - 23 (8 bit)
access : read-write

DATA7 : DATA7
bits : 24 - 31 (8 bit)
access : read-write



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