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ECAP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TSCTR

CAP1

CAP2

CAP3

CAP4

ECCTL1

ECCTL2

ECEINT

ECFLG

ECCLR

ECFRC

CTRPHS


TSCTR

Time-Stamp Counter Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSCTR TSCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSCTR

TSCTR : Time-Stamp Counter
bits : 0 - 31 (32 bit)
access : read-write


CAP1

Capture-1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP1 CAP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP1

CAP1 : CEVT1 counter load
bits : 0 - 31 (32 bit)
access : read-write


CAP2

Capture-2 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP2 CAP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP2

CAP2 : CEVT2 counter load
bits : 0 - 31 (32 bit)
access : read-write


CAP3

Capture-3 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP3 CAP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP3

CAP3 : CEVT3 counter load
bits : 0 - 31 (32 bit)
access : read-write


CAP4

Capture-4 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAP4 CAP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP4

CAP4 : CEVT4 counter load
bits : 0 - 31 (32 bit)
access : read-write


ECCTL1

ECAP Control Register 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCTL1 ECCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP1POL CTRRST1 CAP2POL CTRRST2 CAP3POL CTRRST3 CAP4POL CTRRST4 CAPLDEN PRESCALE FREE_SOFT

CAP1POL : Capture Event 1 Polarity select
bits : 0 - 0 (1 bit)
access : read-write

CTRRST1 : Counter Reset on Capture Event 1
bits : 1 - 1 (1 bit)
access : read-write

CAP2POL : Capture Event 2 Polarity select
bits : 2 - 2 (1 bit)
access : read-write

CTRRST2 : Counter Reset on Capture Event 2
bits : 3 - 3 (1 bit)
access : read-write

CAP3POL : Capture Event 3 Polarity select
bits : 4 - 4 (1 bit)
access : read-write

CTRRST3 : Counter Reset on Capture Event 3
bits : 5 - 5 (1 bit)
access : read-write

CAP4POL : Capture Event 4 Polarity select
bits : 6 - 6 (1 bit)
access : read-write

CTRRST4 : Counter Reset on Capture Event 4
bits : 7 - 7 (1 bit)
access : read-write

CAPLDEN : CAP1-4 registers Load Enable
bits : 8 - 8 (1 bit)
access : read-write

PRESCALE : Event Filter prescale select
bits : 9 - 13 (5 bit)
access : read-write

FREE_SOFT : Emulation Control
bits : 14 - 15 (2 bit)
access : read-write


ECCTL2

ECAP Control Register 2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCTL2 ECCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ONESHT STOP_WRAP RE_ARM TSCTRSTOP SYNCI_EN SYNCO_SEL SWSYNC APWM APWMPOL

ONESHT : One-Shot Mode Enable
bits : 0 - 0 (1 bit)
access : read-write

STOP_WRAP : Stop Value for One-Shot Mode
bits : 1 - 2 (2 bit)
access : read-write

RE_ARM : One-Shot Re-Arming Control
bits : 3 - 3 (1 bit)
access : read-write

TSCTRSTOP : TSCTR Stop Control
bits : 4 - 4 (1 bit)
access : read-write

SYNCI_EN : TSCTR Sync-In Enable
bits : 5 - 5 (1 bit)
access : read-write

SYNCO_SEL : Sync-Out Select
bits : 6 - 7 (2 bit)
access : read-write

SWSYNC : Software-forced Counter Synchronizing
bits : 8 - 8 (1 bit)
access : read-write

APWM : APWM Mode Enable
bits : 9 - 9 (1 bit)
access : read-write

APWMPOL : APWM Output Polarity Select
bits : 10 - 10 (1 bit)
access : read-write


ECEINT

ECAP Interrupt Enable Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECEINT ECEINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEVT1 CEVT2 CEVT3 CEVT4 CTROVF CTR_PRD CTR_CMP

CEVT1 : Capture Event 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CEVT2 : Capture Event 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CEVT3 : Capture Event 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

CEVT4 : Capture Event 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

CTROVF : Counter Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

CTR_PRD : Counter Equal Period Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

CTR_CMP : Counter Equal Compare Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write


ECFLG

ECAP Interrupt Flag Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECFLG ECFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT CEVT1 CEVT2 CEVT3 CEVT4 CTROVF CTR_PRD CTR_CMP

INT : Global Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

CEVT1 : Capture Event 1 Flag
bits : 1 - 1 (1 bit)
access : read-only

CEVT2 : Capture Event 2 Flag
bits : 2 - 2 (1 bit)
access : read-only

CEVT3 : Capture Event 3 Flag
bits : 3 - 3 (1 bit)
access : read-only

CEVT4 : Capture Event 4 Flag
bits : 4 - 4 (1 bit)
access : read-only

CTROVF : Counter Overflow Flag
bits : 5 - 5 (1 bit)
access : read-only

CTR_PRD : Counter Equal Period Flag
bits : 6 - 6 (1 bit)
access : read-only

CTR_CMP : Counter Equal Compare Flag
bits : 7 - 7 (1 bit)
access : read-only


ECCLR

ECAP Interrupt Clear Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCLR ECCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT CEVT1 CEVT2 CEVT3 CEVT4 CTROVF CTR_PRD CTR_CMP

INT : Global Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

CEVT1 : Capture Event 1 Flag
bits : 1 - 1 (1 bit)
access : read-write

CEVT2 : Capture Event 2 Flag
bits : 2 - 2 (1 bit)
access : read-write

CEVT3 : Capture Event 3 Flag
bits : 3 - 3 (1 bit)
access : read-write

CEVT4 : Capture Event 4 Flag
bits : 4 - 4 (1 bit)
access : read-write

CTROVF : Counter Overflow Flag
bits : 5 - 5 (1 bit)
access : read-write

CTR_PRD : Counter Equal Period Flag
bits : 6 - 6 (1 bit)
access : read-write

CTR_CMP : Counter Equal Compare Flag
bits : 7 - 7 (1 bit)
access : read-write


ECFRC

ECAP Interrupt Forcing Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECFRC ECFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEVT1 CEVT2 CEVT3 CEVT4 CTROVF CTR_PRD CTR_CMP

CEVT1 : Force Capture Event 1
bits : 1 - 1 (1 bit)
access : read-write

CEVT2 : Force Capture Event 2
bits : 2 - 2 (1 bit)
access : read-write

CEVT3 : Force Capture Event 3
bits : 3 - 3 (1 bit)
access : read-write

CEVT4 : Force Capture Event 4
bits : 4 - 4 (1 bit)
access : read-write

CTROVF : Force Counter Overflow
bits : 5 - 5 (1 bit)
access : read-write

CTR_PRD : Force Counter Equal Period Interrupt
bits : 6 - 6 (1 bit)
access : read-write

CTR_CMP : Force Counter Equal Compare Interrupt
bits : 7 - 7 (1 bit)
access : read-write


CTRPHS

Counter Phase Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRPHS CTRPHS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRPHS

CTRPHS : Counter phase value
bits : 0 - 31 (32 bit)
access : read-write



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