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EQEP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

QPOSCNT

QPOSMAX

QPOSCMP

QPOSILAT

QPOSSLAT

QPOSLAT

QUTMR

QUPRD

QWDTMR

QWDPRD

QDECCTL

QEPCTL

QCAPCTL

QPOSCTL

QEINT

QFLG

QCLR

QFRC

QEPSTS

QCTMR

QCPRD

QCTMRLAT

QPOSINIT

QCPRDLAT


QPOSCNT

eQEP Position Counter
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSCNT QPOSCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSMAX

eQEP Maximum Position Count
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSMAX QPOSMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSCMP

eQEP Position-compare
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSCMP QPOSCMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSILAT

eQEP Index Position Latch
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSILAT QPOSILAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSSLAT

eQEP Strobe Position Latch
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSSLAT QPOSSLAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSLAT

eQEP Position Latch
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSLAT QPOSLAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QUTMR

QEP Unit Timer
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUTMR QUTMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QUPRD

eQEP Unit Period Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUPRD QUPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QWDTMR

eQEP Watchdog Timer
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QWDTMR QWDTMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QWDPRD

eQEP Watchdog Period Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QWDPRD QWDPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QDECCTL

eQEP Decoder Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDECCTL QDECCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSP QIP QBP QAP IGATE SWAP XCR SPSEL SOEN QSRC

QSP : QEPS input polarity
bits : 5 - 5 (1 bit)
access : read-write

QIP : QEPI input polarity
bits : 6 - 6 (1 bit)
access : read-write

QBP : QEPB input polarity
bits : 7 - 7 (1 bit)
access : read-write

QAP : QEPA input polarity
bits : 8 - 8 (1 bit)
access : read-write

IGATE : Index pulse gating option
bits : 9 - 9 (1 bit)
access : read-write

SWAP : Swap quadrature clock inputs
bits : 10 - 10 (1 bit)
access : read-write

XCR : External clock rate
bits : 11 - 11 (1 bit)
access : read-write

SPSEL : Sync output pin selection
bits : 12 - 12 (1 bit)
access : read-write

SOEN : Sync output-enable
bits : 13 - 13 (1 bit)
access : read-write

QSRC : Position-counter source selection
bits : 14 - 15 (2 bit)
access : read-write


QEPCTL

eQEP Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QEPCTL QEPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDE UTE QCLM QPEN IEL SEL SWI IEI SEI PCRM FREE_SOFT

WDE : eQEP watchdog enable
bits : 0 - 0 (1 bit)
access : read-write

UTE : eQEP unit timer enable
bits : 1 - 1 (1 bit)
access : read-write

QCLM : eQEP capture latch mode
bits : 2 - 2 (1 bit)
access : read-write

QPEN : Quadrature position counter enable/software reset
bits : 3 - 3 (1 bit)
access : read-write

IEL : Index event latch of position counter
bits : 4 - 5 (2 bit)
access : read-write

SEL : Strobe event latch of position counter
bits : 6 - 6 (1 bit)
access : read-write

SWI : Software initialization of position counter
bits : 7 - 7 (1 bit)
access : read-write

IEI : Index event initialization of position counter
bits : 8 - 9 (2 bit)
access : read-write

SEI : Strobe event initialization of position counter
bits : 10 - 11 (2 bit)
access : read-write

PCRM : Position counter reset mode
bits : 12 - 13 (2 bit)
access : read-write

FREE_SOFT : Emulation Control Bits
bits : 14 - 15 (2 bit)
access : read-write


QCAPCTL

eQEP Capture Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCAPCTL QCAPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPPS CCPS CEN

UPPS : Unit position event prescaler
bits : 0 - 3 (4 bit)
access : read-write

CCPS : eQEP capture timer clock prescaler
bits : 4 - 6 (3 bit)
access : read-write

CEN : Enable eQEP capture
bits : 15 - 15 (1 bit)
access : read-write


QPOSCTL

eQEP Position-compare Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSCTL QPOSCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCSPW PCE PCPOL PCLOAD PCSHDW

PCSPW : Select-position-compare sync output pulse width
bits : 0 - 11 (12 bit)
access : read-write

PCE : Position-compare enable/disable
bits : 12 - 12 (1 bit)
access : read-write

PCPOL : Polarity of sync output
bits : 13 - 13 (1 bit)
access : read-write

PCLOAD : Position-compare shadow load mode
bits : 14 - 14 (1 bit)
access : read-write

PCSHDW : Position-compare shadow enable
bits : 15 - 15 (1 bit)
access : read-write


QEINT

eQEP Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QEINT QEINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCE QPE QDC WTO PCU PCO PCR PCM SEL IEL UTO

PCE : Position counter error interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

QPE : Quadrature phase error interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

QDC : Quadrature direction change interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

WTO : Watchdog time out interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

PCU : Position counter underflow interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

PCO : Position counter overflow interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

PCR : Position-compare ready interrupt enable
bits : 7 - 7 (1 bit)
access : read-write

PCM : Position-compare match interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

SEL : Strobe event latch interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

IEL : Index event latch interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

UTO : Unit time out interrupt enable
bits : 11 - 11 (1 bit)
access : read-write


QFLG

eQEP Interrupt Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QFLG QFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT PCE QPE QDC WTO PCU PCO PCR PCM SEL IEL UTO

INT : Global interrupt status flag
bits : 0 - 0 (1 bit)
access : read-only

PCE : Position counter error interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

QPE : Quadrature phase error interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

QDC : Quadrature direction change interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

WTO : Watchdog time out interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

PCU : Position counter underflow interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

PCO : Position counter overflow interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

PCR : Position-compare ready interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

PCM : Position-compare match interrupt flag
bits : 8 - 8 (1 bit)
access : read-only

SEL : Strobe event latch interrupt flag
bits : 9 - 9 (1 bit)
access : read-only

IEL : Index event latch interrupt flag
bits : 10 - 10 (1 bit)
access : read-only

UTO : Unit time out interrupt flag
bits : 11 - 11 (1 bit)
access : read-only


QCLR

eQEP Interrupt Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCLR QCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT PCE QPE QDC WTO PCU PCO PCR PCM SEL IEL UTO

INT : Clear Global interrupt status flag
bits : 0 - 0 (1 bit)
access : read-write

PCE : Clear Position counter error interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

QPE : Clear Quadrature phase error interrupt flag
bits : 2 - 2 (1 bit)
access : read-write

QDC : Clear Quadrature direction change interrupt flag
bits : 3 - 3 (1 bit)
access : read-write

WTO : Clear Watchdog time out interrupt flag
bits : 4 - 4 (1 bit)
access : read-write

PCU : Clear Position counter underflow interrupt flag
bits : 5 - 5 (1 bit)
access : read-write

PCO : Clear Position counter overflow interrupt flag
bits : 6 - 6 (1 bit)
access : read-write

PCR : Clear Position-compare ready interrupt flag
bits : 7 - 7 (1 bit)
access : read-write

PCM : Clear Position-compare match interrupt flag
bits : 8 - 8 (1 bit)
access : read-write

SEL : Clear Strobe event latch interrupt flag
bits : 9 - 9 (1 bit)
access : read-write

IEL : Clear Index event latch interrupt flag
bits : 10 - 10 (1 bit)
access : read-write

UTO : Clear Unit time out interrupt flag
bits : 11 - 11 (1 bit)
access : read-write


QFRC

eQEP Interrupt Force Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QFRC QFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCE QPE QDC WTO PCU PCO PCR PCM SEL IEL UTO

PCE : Force Position counter error interrupt
bits : 1 - 1 (1 bit)
access : read-write

QPE : Force Quadrature phase error interrupt
bits : 2 - 2 (1 bit)
access : read-write

QDC : Force Quadrature direction change interrupt
bits : 3 - 3 (1 bit)
access : read-write

WTO : Force Watchdog time out interrupt
bits : 4 - 4 (1 bit)
access : read-write

PCU : Force Position counter underflow interrupt
bits : 5 - 5 (1 bit)
access : read-write

PCO : Force Position counter overflow interrupt
bits : 6 - 6 (1 bit)
access : read-write

PCR : Force Position-compare ready interrupt
bits : 7 - 7 (1 bit)
access : read-write

PCM : Force Position-compare match interrupt
bits : 8 - 8 (1 bit)
access : read-write

SEL : Force Strobe event latch interrupt
bits : 9 - 9 (1 bit)
access : read-write

IEL : Force Index event latch interrupt
bits : 10 - 10 (1 bit)
access : read-write

UTO : Force Unit time out interrupt
bits : 11 - 11 (1 bit)
access : read-write


QEPSTS

eQEP Status Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QEPSTS QEPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCEF FIMF CDEF COEF QDLF QDF FIDF UPEVNT

PCEF : Position counter error flag
bits : 0 - 0 (1 bit)
access : read-only

FIMF : First index marker flag
bits : 1 - 1 (1 bit)
access : read-write

CDEF : Capture direction error flag
bits : 2 - 2 (1 bit)
access : read-write

COEF : Capture overflow error flag
bits : 3 - 3 (1 bit)
access : read-write

QDLF : eQEP direction latch flag
bits : 4 - 4 (1 bit)
access : read-only

QDF : Quadrature direction flag
bits : 5 - 5 (1 bit)
access : read-only

FIDF : Direction on the first index marker
bits : 6 - 6 (1 bit)
access : read-only

UPEVNT : Unit position event flag
bits : 7 - 7 (1 bit)
access : read-write


QCTMR

eQEP Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCTMR QCTMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QCPRD

eQEP Capture Period Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCPRD QCPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QCTMRLAT

eQEP Capture Timer Latch
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

QCTMRLAT QCTMRLAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QPOSINIT

eQEP Initialization Position Count
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QPOSINIT QPOSINIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

QCPRDLAT

eQEP Capture Period Latch
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCPRDLAT QCPRDLAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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