\n

PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TBCTL

TBCTR

TBPRD

CMPCTL

CMPA

CMPB

AQCTLA

AQCTLB

AQSFRC

AQCSFRC

DBCTL

TBSTS

DBRED

DBFED

TZSEL

TZDCSEL

TZCTL

TZEINT

TZFLG

TZCLR

TZFRC

ETSEL

ETPS

ETFLG

ETCLR

ETFRC

PCCTL

TBPRDM

CMPAM

TBPHS

DCTRIPSEL

DCACTL

DCBCTL

DCFCTL

DCCAPCTL

DCFOFFSET

DCFOFFSETCNT

DCFWINDOW

DCFWINDOWCNT

DCCAP


TBCTL

Time-Base Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCTL TBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRMODE PHSEN PRDLD SYNCOSEL SWFSYNC HSPCLKDIV CLKDIV PHSDIR FREE_SOFT

CTRMODE : Counter Mode
bits : 0 - 1 (2 bit)
access : read-write

PHSEN : Counter Register Load From Phase Register Enable
bits : 2 - 2 (1 bit)
access : read-write

PRDLD : Active Period Register Load From Shadow Register Select
bits : 3 - 3 (1 bit)
access : read-write

SYNCOSEL : Synchronization Output Select
bits : 4 - 5 (2 bit)
access : read-write

SWFSYNC : Software Forced Synchronization Pulse
bits : 6 - 6 (1 bit)
access : read-write

HSPCLKDIV : High Speed Time-base Clock Prescale Bits
bits : 7 - 9 (3 bit)
access : read-write

CLKDIV : Time-base Clock Prescale Bits
bits : 10 - 12 (3 bit)
access : read-write

PHSDIR : Phase Direction Bit
bits : 13 - 13 (1 bit)
access : read-write

FREE_SOFT : Emulation Mode Bits
bits : 14 - 15 (2 bit)
access : read-write


TBCTR

Time-Base Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCTR TBCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBPRD

Time-Base Period Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBPRD TBPRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CMPCTL

Counter-Compare Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCTL CMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOADAMODE LOADBMODE SHDWAMODE SHDWBMODE SHDWAFULL SHDWBFULL

LOADAMODE : Active CMPA Load From Shadow Select Mode
bits : 0 - 1 (2 bit)
access : read-write

LOADBMODE : Active CMPB Load From Shadow Select Mode
bits : 2 - 3 (2 bit)
access : read-write

SHDWAMODE : CMPA Register Operating Mode
bits : 4 - 4 (1 bit)
access : read-write

SHDWBMODE : CMPB Register Operating Mode
bits : 6 - 6 (1 bit)
access : read-write

SHDWAFULL : CMPA Shadow Register Full Status Flag
bits : 8 - 8 (1 bit)
access : read-only

SHDWBFULL : CMPB Shadow Register Full Status Flag
bits : 9 - 9 (1 bit)
access : read-only


CMPA

Counter-Compare A Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPA CMPA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CMPB

Counter-Compare B Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPB CMPB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AQCTLA

Action-Qualifier Output A Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AQCTLA AQCTLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZRO PRU CAU CAD CBU CBD

ZRO : Action when counter equals zero
bits : 0 - 1 (2 bit)
access : read-write

PRU : Action when the counter equals the period
bits : 2 - 3 (2 bit)
access : read-write

CAU : Action when the counter equals the active CMPA register and the counter is incrementing
bits : 4 - 5 (2 bit)
access : read-write

CAD : Action when the counter equals the active CMPA register and the counter is decrementing
bits : 6 - 7 (2 bit)
access : read-write

CBU : Action when the counter equals the active CMPB register and the counter is incrementing
bits : 8 - 9 (2 bit)
access : read-write

CBD : Action when the time-base counter equals the active CMPB register and the counter is decrementing
bits : 10 - 11 (2 bit)
access : read-write


AQCTLB

Action-Qualifier Output B Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AQCTLB AQCTLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZRO PRU CAU CAD CBU CBD

ZRO : Action when counter equals zero
bits : 0 - 1 (2 bit)
access : read-write

PRU : Action when the counter equals the period
bits : 2 - 3 (2 bit)
access : read-write

CAU : Action when the counter equals the active CMPA register and the counter is incrementing
bits : 4 - 5 (2 bit)
access : read-write

CAD : Action when the counter equals the active CMPA register and the counter is decrementing
bits : 6 - 7 (2 bit)
access : read-write

CBU : Action when the counter equals the active CMPB register and the counter is incrementing
bits : 8 - 9 (2 bit)
access : read-write

CBD : Action when the time-base counter equals the active CMPB register and the counter is decrementing
bits : 10 - 11 (2 bit)
access : read-write


AQSFRC

Action-Qualifier Software Force Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AQSFRC AQSFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTSFA OTSFA ACTSFB OTSFB RLDCSF

ACTSFA : Action When One-Time Software Force A Is Invoked
bits : 0 - 1 (2 bit)
access : read-write

OTSFA : One-Time Software Forced Event on Output A
bits : 2 - 2 (1 bit)
access : read-write

ACTSFB : Action when One-Time Software Force B Is invoked
bits : 3 - 4 (2 bit)
access : read-write

OTSFB : One-Time Software Forced Event on Output B
bits : 5 - 5 (1 bit)
access : read-write

RLDCSF : AQCSFRC Active Register Reload From Shadow Options
bits : 6 - 7 (2 bit)
access : read-write


AQCSFRC

Action-Qualifier Continuous Software Force Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AQCSFRC AQCSFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSFA CSFB

CSFA : Continuous Software Force on Output A
bits : 0 - 1 (2 bit)
access : read-write

CSFB : Continuous Software Force on Output B
bits : 2 - 3 (2 bit)
access : read-write


DBCTL

Dead-Band Generator Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCTL DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_MODE POLSEL IN_MODE HALFCYCLE

OUT_MODE : Dead-band Output Mode Control
bits : 0 - 1 (2 bit)
access : read-write

POLSEL : Polarity Select Control
bits : 2 - 3 (2 bit)
access : read-write

IN_MODE : Dead Band Input Mode Control
bits : 4 - 5 (2 bit)
access : read-write

HALFCYCLE : Half Cycle Clocking Enable Bit
bits : 15 - 15 (1 bit)
access : read-write


TBSTS

Time-Base Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBSTS TBSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRDIR SYNCI CTRMAX

CTRDIR : Time-Base Counter Direction Status Bit
bits : 0 - 0 (1 bit)
access : read-only

SYNCI : Input Synchronization Latched Status Bit
bits : 1 - 1 (1 bit)
access : read-write

CTRMAX : Time-Base Counter Max Latched Status Bit
bits : 2 - 2 (1 bit)
access : read-write


DBRED

Dead-Band Generator Rising Edge Delay Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBRED DBRED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DBFED

Dead-Band Generator Falling Edge Delay Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBFED DBFED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TZSEL

Trip-Zone Submodule Select Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZSEL TZSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBC0 CBC1 CBC2 CBC3 CBC4 CBC5 DCAEVT2 DCBEVT2 OSHT0 OSHT1 OSHT2 OSHT3 OSHT4 OSHT5 DCAEVT1 DCBEVT1

CBC0 : A0 Event Source Select
bits : 0 - 0 (1 bit)
access : read-write

CBC1 : B0 Event Source Select
bits : 1 - 1 (1 bit)
access : read-write

CBC2 : A0 Event Source Select
bits : 2 - 2 (1 bit)
access : read-write

CBC3 : B0 Event Source Select
bits : 3 - 3 (1 bit)
access : read-write

CBC4 : A0 Event Source Select
bits : 4 - 4 (1 bit)
access : read-write

CBC5 : B0 Event Source Select
bits : 5 - 5 (1 bit)
access : read-write

DCAEVT2 : Digital Compare Output A Event 2 Select
bits : 6 - 6 (1 bit)
access : read-write

DCBEVT2 : Digital Compare Output B Event 2 Select
bits : 7 - 7 (1 bit)
access : read-write

OSHT0 : A0 Event Source Select
bits : 8 - 8 (1 bit)
access : read-write

OSHT1 : B0 Event Source Select
bits : 9 - 9 (1 bit)
access : read-write

OSHT2 : A0 Event Source Select
bits : 10 - 10 (1 bit)
access : read-write

OSHT3 : B0 Event Source Select
bits : 11 - 11 (1 bit)
access : read-write

OSHT4 : A0 Event Source Select
bits : 12 - 12 (1 bit)
access : read-write

OSHT5 : B0 Event Source Select
bits : 13 - 13 (1 bit)
access : read-write

DCAEVT1 : Digital Compare Output A Event 1 Select
bits : 14 - 14 (1 bit)
access : read-write

DCBEVT1 : Digital Compare Output B Event 1 Select
bits : 15 - 15 (1 bit)
access : read-write


TZDCSEL

Trip Zone Digital Compare Event Select Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZDCSEL TZDCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2

DCAEVT1 : Digital Compare Output A Event 1 Selection
bits : 0 - 2 (3 bit)
access : read-write

DCAEVT2 : Digital Compare Output A Event 2 Selection
bits : 3 - 5 (3 bit)
access : read-write

DCBEVT1 : Digital Compare Output B Event 1 Selection
bits : 6 - 8 (3 bit)
access : read-write

DCBEVT2 : Digital Compare Output B Event 2 Selection
bits : 9 - 11 (3 bit)
access : read-write


TZCTL

Trip-Zone Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZCTL TZCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TZA TZB DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2 SYNC_OUTEN

TZA : Action on output EPWMxA
bits : 0 - 1 (2 bit)
access : read-write

TZB : Action on output EPWMxB
bits : 2 - 3 (2 bit)
access : read-write

DCAEVT1 : Digital Compare Output A Event 1 Action On EPWMxA
bits : 4 - 5 (2 bit)
access : read-write

DCAEVT2 : Digital Compare Output A Event 2 Action On EPWMxA
bits : 6 - 7 (2 bit)
access : read-write

DCBEVT1 : Digital Compare Output B Event 1 Action On EPWMxB
bits : 8 - 9 (2 bit)
access : read-write

DCBEVT2 : Digital Compare Output B Event 2 Action On EPWMxB
bits : 10 - 11 (2 bit)
access : read-write

SYNC_OUTEN : PWM output sync enable
bits : 31 - 31 (1 bit)
access : read-write


TZEINT

Trip-Zone Enable Interrupt Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZEINT TZEINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBC OST DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2

CBC : Trip-zone Cycle-by-Cycle Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

OST : Trip-zone One-Shot Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

DCAEVT1 : Digital Comparator Output A Event 1 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

DCAEVT2 : Digital Comparator Output A Event 2 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

DCBEVT1 : Digital Comparator Output B Event 1 Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DCBEVT2 : Digital Comparator Output B Event 2 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write


TZFLG

Trip-Zone Flag Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TZFLG TZFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT CBC OST DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2

INT : Latched Trip Interrupt Status Flag
bits : 0 - 0 (1 bit)
access : read-only

CBC : Latched Status Flag for Cycle-By-Cycle Trip Event
bits : 1 - 1 (1 bit)
access : read-only

OST : Latched Status Flag for A One-Shot Trip Event
bits : 2 - 2 (1 bit)
access : read-only

DCAEVT1 : Latched Status Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-only

DCAEVT2 : Latched Status Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-only

DCBEVT1 : Latched Status Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-only

DCBEVT2 : Latched Status Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-only


TZCLR

Trip-Zone Clear Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZCLR TZCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT CBC OST DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2

INT : Global Interrupt Clear Flag
bits : 0 - 0 (1 bit)
access : read-write

CBC : Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
bits : 1 - 1 (1 bit)
access : read-write

OST : Clear Flag for One-Shot Trip Latch
bits : 2 - 2 (1 bit)
access : read-write

DCAEVT1 : Clear Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-write

DCAEVT2 : Clear Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-write

DCBEVT1 : Clear Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-write

DCBEVT2 : Clear Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-write


TZFRC

Trip-Zone Force Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TZFRC TZFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBC OST DCAEVT1 DCAEVT2 DCBEVT1 DCBEVT2

CBC : Force a Cycle-by-Cycle Trip Event via Software
bits : 1 - 1 (1 bit)
access : read-write

OST : Force a One-Shot Trip Event via Software
bits : 2 - 2 (1 bit)
access : read-write

DCAEVT1 : Force Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-write

DCAEVT2 : Force Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-write

DCBEVT1 : Force Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-write

DCBEVT2 : Force Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-write


ETSEL

Event-Trigger Selection Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETSEL ETSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTESEL INTEN SOCASEL SOCAEN SOCBSEL SOCBEN

INTESEL : ePWM Interrupt (EPWMx_INT) Selection Options
bits : 0 - 2 (3 bit)
access : read-write

INTEN : Enable ePWM Interrupt (EPWMx_INT) Generation
bits : 3 - 3 (1 bit)
access : read-write

SOCASEL : EPWMxSOCA Selection Options
bits : 8 - 10 (3 bit)
access : read-write

SOCAEN : Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
bits : 11 - 11 (1 bit)
access : read-write

SOCBSEL : EPWMxSOCB Selection Options
bits : 12 - 14 (3 bit)
access : read-write

SOCBEN : Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
bits : 15 - 15 (1 bit)
access : read-write


ETPS

Event-Trigger Prescale Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETPS ETPS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPRD INTCNT SOCAPRD SOCACNT SOCBPRD SOCBCNT

INTPRD : ePWM Interrupt (EPWMx_INT) Period Select
bits : 0 - 1 (2 bit)
access : read-write

INTCNT : ePWM Interrupt Event (EPWMx_INT) Counter Register
bits : 2 - 3 (2 bit)
access : read-only

SOCAPRD : ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select
bits : 8 - 9 (2 bit)
access : read-write

SOCACNT : ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register
bits : 10 - 11 (2 bit)
access : read-only

SOCBPRD : ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select
bits : 12 - 13 (2 bit)
access : read-write

SOCBCNT : ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register
bits : 14 - 15 (2 bit)
access : read-only


ETFLG

Event-Trigger Flag Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETFLG ETFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT SOCA SOCB CTRDIR

INT : Latched ePWM Interrupt (EPWMx_INT) Status Flag
bits : 0 - 0 (1 bit)
access : read-only

SOCA : Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
bits : 2 - 2 (1 bit)
access : read-only

SOCB : Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
bits : 3 - 3 (1 bit)
access : read-only

CTRDIR : PWM Counter Direction
bits : 31 - 31 (1 bit)
access : read-only


ETCLR

Event-Trigger Clear Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETCLR ETCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT SOCA SOCB

INT : ePWM Interrupt (EPWMx_INT) Flag Clear Bit
bits : 0 - 0 (1 bit)
access : read-write

SOCA : ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
bits : 2 - 2 (1 bit)
access : read-write

SOCB : ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit
bits : 3 - 3 (1 bit)
access : read-write


ETFRC

Event-Trigger Force Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETFRC ETFRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT SOCA SOCB

INT : INT Force Bit
bits : 0 - 0 (1 bit)
access : read-write

SOCA : SOCA Force Bit
bits : 2 - 2 (1 bit)
access : read-write

SOCB : SOCB Force Bit
bits : 3 - 3 (1 bit)
access : read-write


PCCTL

PWM-Chopper Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCCTL PCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHPEN OSHTWTH CHPFREQ CHPDUTY CHPFREQ1

CHPEN : PWM-chopping Enable
bits : 0 - 0 (1 bit)
access : read-write

OSHTWTH : One-Shot Pulse Width
bits : 1 - 4 (4 bit)
access : read-write

CHPFREQ : Chopping Clock Frequency
bits : 5 - 7 (3 bit)
access : read-write

CHPDUTY : Chopping Clock Duty Cycle
bits : 8 - 10 (3 bit)
access : read-write

CHPFREQ1 : Chopping Clock Frequency1
bits : 11 - 15 (5 bit)
access : read-write


TBPRDM

Time Base Period register Mirror
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBPRDM TBPRDM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CMPAM

Compare Register A Mirror
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPAM CMPAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBPHS

Time-Base Phase Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBPHS TBPHS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCTRIPSEL

Digital Compare Trip Select
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTRIPSEL DCTRIPSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCAHCOMPSEL DCALCOMPSEL DCBHCOMPSEL DCBLCOMPSEL

DCAHCOMPSEL : Digital Compare A High Input Select
bits : 0 - 3 (4 bit)
access : read-write

DCALCOMPSEL : Digital Compare A Low Input Select
bits : 4 - 7 (4 bit)
access : read-write

DCBHCOMPSEL : Digital Compare B High Input Select
bits : 8 - 11 (4 bit)
access : read-write

DCBLCOMPSEL : Digital Compare B Low Input Select
bits : 12 - 15 (4 bit)
access : read-write


DCACTL

Digital Compare A Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCACTL DCACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVT1SRCSEL EVT1FRCSYNCSEL EVT1SOCE EVT1SYNCE EVT2SRCSEL EVT2FRCSYNCSEL

EVT1SRCSEL : DCAEVT1 Source Signal Select
bits : 0 - 0 (1 bit)
access : read-write

EVT1FRCSYNCSEL : DCAEVT1 Force Synchronization Signal Select
bits : 1 - 1 (1 bit)
access : read-write

EVT1SOCE : DCAEVT1 SOC, Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write

EVT1SYNCE : DCAEVT1 SYNC, Enable/Disable
bits : 3 - 3 (1 bit)
access : read-write

EVT2SRCSEL : DCAEVT2 Source Signal Select
bits : 8 - 8 (1 bit)
access : read-write

EVT2FRCSYNCSEL : DCAEVT2 Force Synchronization Signal Select
bits : 9 - 9 (1 bit)
access : read-write


DCBCTL

Digital Compare B Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCBCTL DCBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVT1SRCSEL EVT1FRCSYNCSEL EVT1SOCE EVT1SYNCE EVT2SRCSEL EVT2FRCSYNCSEL

EVT1SRCSEL : DCBEVT1 Source Signal Select
bits : 0 - 0 (1 bit)
access : read-write

EVT1FRCSYNCSEL : DCBEVT1 Force Synchronization Signal Select
bits : 1 - 1 (1 bit)
access : read-write

EVT1SOCE : DCBEVT1 SOC, Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write

EVT1SYNCE : DCBEVT1 SYNC, Enable/Disable
bits : 3 - 3 (1 bit)
access : read-write

EVT2SRCSEL : DCBEVT2 Source Signal Select
bits : 8 - 8 (1 bit)
access : read-write

EVT2FRCSYNCSEL : DCBEVT2 Force Synchronization Signal Select
bits : 9 - 9 (1 bit)
access : read-write


DCFCTL

Digital Compare Filter Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFCTL DCFCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCSEL BLANKE BLANKINV PULSESEL

SRCSEL : Filter Block Signal Source Select
bits : 0 - 1 (2 bit)
access : read-write

BLANKE : Blanking Window Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write

BLANKINV : Blanking Window Inversion
bits : 3 - 3 (1 bit)
access : read-write

PULSESEL : Pulse Select For Blanking and Capture Alignment
bits : 4 - 5 (2 bit)
access : read-write


DCCAPCTL

Digital Compare Capture Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCCAPCTL DCCAPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPE SHDWMODE

CAPE : TBCTR Counter Capture Enable/Disable
bits : 0 - 0 (1 bit)
access : read-write

SHDWMODE : TBCTR Counter Capture Shadow Select Mode
bits : 1 - 1 (1 bit)
access : read-write


DCFOFFSET

Digital Compare Filter Offset Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFOFFSET DCFOFFSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCFOFFSETCNT

Digital Compare Filter Offset Counter Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCFOFFSETCNT DCFOFFSETCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCFWINDOW

Digital Compare Filter Window Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFWINDOW DCFWINDOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDOW

WINDOW : Blanking Window Width
bits : 0 - 7 (8 bit)
access : read-write


DCFWINDOWCNT

Digital Compare Filter Window Counter Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCFWINDOWCNT DCFWINDOWCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDOWCNT

WINDOWCNT : Blanking Window Counter
bits : 0 - 7 (8 bit)
access : read-only


DCCAP

Digital Compare Counter Capture Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCCAP DCCAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.