\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Time-Base Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRMODE : Counter Mode
bits : 0 - 1 (2 bit)
access : read-write
PHSEN : Counter Register Load From Phase Register Enable
bits : 2 - 2 (1 bit)
access : read-write
PRDLD : Active Period Register Load From Shadow Register Select
bits : 3 - 3 (1 bit)
access : read-write
SYNCOSEL : Synchronization Output Select
bits : 4 - 5 (2 bit)
access : read-write
SWFSYNC : Software Forced Synchronization Pulse
bits : 6 - 6 (1 bit)
access : read-write
HSPCLKDIV : High Speed Time-base Clock Prescale Bits
bits : 7 - 9 (3 bit)
access : read-write
CLKDIV : Time-base Clock Prescale Bits
bits : 10 - 12 (3 bit)
access : read-write
PHSDIR : Phase Direction Bit
bits : 13 - 13 (1 bit)
access : read-write
FREE_SOFT : Emulation Mode Bits
bits : 14 - 15 (2 bit)
access : read-write
Time-Base Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Time-Base Period Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Counter-Compare Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOADAMODE : Active CMPA Load From Shadow Select Mode
bits : 0 - 1 (2 bit)
access : read-write
LOADBMODE : Active CMPB Load From Shadow Select Mode
bits : 2 - 3 (2 bit)
access : read-write
SHDWAMODE : CMPA Register Operating Mode
bits : 4 - 4 (1 bit)
access : read-write
SHDWBMODE : CMPB Register Operating Mode
bits : 6 - 6 (1 bit)
access : read-write
SHDWAFULL : CMPA Shadow Register Full Status Flag
bits : 8 - 8 (1 bit)
access : read-only
SHDWBFULL : CMPB Shadow Register Full Status Flag
bits : 9 - 9 (1 bit)
access : read-only
Counter-Compare A Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Counter-Compare B Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Action-Qualifier Output A Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZRO : Action when counter equals zero
bits : 0 - 1 (2 bit)
access : read-write
PRU : Action when the counter equals the period
bits : 2 - 3 (2 bit)
access : read-write
CAU : Action when the counter equals the active CMPA register and the counter is incrementing
bits : 4 - 5 (2 bit)
access : read-write
CAD : Action when the counter equals the active CMPA register and the counter is decrementing
bits : 6 - 7 (2 bit)
access : read-write
CBU : Action when the counter equals the active CMPB register and the counter is incrementing
bits : 8 - 9 (2 bit)
access : read-write
CBD : Action when the time-base counter equals the active CMPB register and the counter is decrementing
bits : 10 - 11 (2 bit)
access : read-write
Action-Qualifier Output B Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZRO : Action when counter equals zero
bits : 0 - 1 (2 bit)
access : read-write
PRU : Action when the counter equals the period
bits : 2 - 3 (2 bit)
access : read-write
CAU : Action when the counter equals the active CMPA register and the counter is incrementing
bits : 4 - 5 (2 bit)
access : read-write
CAD : Action when the counter equals the active CMPA register and the counter is decrementing
bits : 6 - 7 (2 bit)
access : read-write
CBU : Action when the counter equals the active CMPB register and the counter is incrementing
bits : 8 - 9 (2 bit)
access : read-write
CBD : Action when the time-base counter equals the active CMPB register and the counter is decrementing
bits : 10 - 11 (2 bit)
access : read-write
Action-Qualifier Software Force Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTSFA : Action When One-Time Software Force A Is Invoked
bits : 0 - 1 (2 bit)
access : read-write
OTSFA : One-Time Software Forced Event on Output A
bits : 2 - 2 (1 bit)
access : read-write
ACTSFB : Action when One-Time Software Force B Is invoked
bits : 3 - 4 (2 bit)
access : read-write
OTSFB : One-Time Software Forced Event on Output B
bits : 5 - 5 (1 bit)
access : read-write
RLDCSF : AQCSFRC Active Register Reload From Shadow Options
bits : 6 - 7 (2 bit)
access : read-write
Action-Qualifier Continuous Software Force Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSFA : Continuous Software Force on Output A
bits : 0 - 1 (2 bit)
access : read-write
CSFB : Continuous Software Force on Output B
bits : 2 - 3 (2 bit)
access : read-write
Dead-Band Generator Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_MODE : Dead-band Output Mode Control
bits : 0 - 1 (2 bit)
access : read-write
POLSEL : Polarity Select Control
bits : 2 - 3 (2 bit)
access : read-write
IN_MODE : Dead Band Input Mode Control
bits : 4 - 5 (2 bit)
access : read-write
HALFCYCLE : Half Cycle Clocking Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Time-Base Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRDIR : Time-Base Counter Direction Status Bit
bits : 0 - 0 (1 bit)
access : read-only
SYNCI : Input Synchronization Latched Status Bit
bits : 1 - 1 (1 bit)
access : read-write
CTRMAX : Time-Base Counter Max Latched Status Bit
bits : 2 - 2 (1 bit)
access : read-write
Dead-Band Generator Rising Edge Delay Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Dead-Band Generator Falling Edge Delay Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Trip-Zone Submodule Select Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBC0 : A0 Event Source Select
bits : 0 - 0 (1 bit)
access : read-write
CBC1 : B0 Event Source Select
bits : 1 - 1 (1 bit)
access : read-write
CBC2 : A0 Event Source Select
bits : 2 - 2 (1 bit)
access : read-write
CBC3 : B0 Event Source Select
bits : 3 - 3 (1 bit)
access : read-write
CBC4 : A0 Event Source Select
bits : 4 - 4 (1 bit)
access : read-write
CBC5 : B0 Event Source Select
bits : 5 - 5 (1 bit)
access : read-write
DCAEVT2 : Digital Compare Output A Event 2 Select
bits : 6 - 6 (1 bit)
access : read-write
DCBEVT2 : Digital Compare Output B Event 2 Select
bits : 7 - 7 (1 bit)
access : read-write
OSHT0 : A0 Event Source Select
bits : 8 - 8 (1 bit)
access : read-write
OSHT1 : B0 Event Source Select
bits : 9 - 9 (1 bit)
access : read-write
OSHT2 : A0 Event Source Select
bits : 10 - 10 (1 bit)
access : read-write
OSHT3 : B0 Event Source Select
bits : 11 - 11 (1 bit)
access : read-write
OSHT4 : A0 Event Source Select
bits : 12 - 12 (1 bit)
access : read-write
OSHT5 : B0 Event Source Select
bits : 13 - 13 (1 bit)
access : read-write
DCAEVT1 : Digital Compare Output A Event 1 Select
bits : 14 - 14 (1 bit)
access : read-write
DCBEVT1 : Digital Compare Output B Event 1 Select
bits : 15 - 15 (1 bit)
access : read-write
Trip Zone Digital Compare Event Select Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCAEVT1 : Digital Compare Output A Event 1 Selection
bits : 0 - 2 (3 bit)
access : read-write
DCAEVT2 : Digital Compare Output A Event 2 Selection
bits : 3 - 5 (3 bit)
access : read-write
DCBEVT1 : Digital Compare Output B Event 1 Selection
bits : 6 - 8 (3 bit)
access : read-write
DCBEVT2 : Digital Compare Output B Event 2 Selection
bits : 9 - 11 (3 bit)
access : read-write
Trip-Zone Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZA : Action on output EPWMxA
bits : 0 - 1 (2 bit)
access : read-write
TZB : Action on output EPWMxB
bits : 2 - 3 (2 bit)
access : read-write
DCAEVT1 : Digital Compare Output A Event 1 Action On EPWMxA
bits : 4 - 5 (2 bit)
access : read-write
DCAEVT2 : Digital Compare Output A Event 2 Action On EPWMxA
bits : 6 - 7 (2 bit)
access : read-write
DCBEVT1 : Digital Compare Output B Event 1 Action On EPWMxB
bits : 8 - 9 (2 bit)
access : read-write
DCBEVT2 : Digital Compare Output B Event 2 Action On EPWMxB
bits : 10 - 11 (2 bit)
access : read-write
SYNC_OUTEN : PWM output sync enable
bits : 31 - 31 (1 bit)
access : read-write
Trip-Zone Enable Interrupt Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBC : Trip-zone Cycle-by-Cycle Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
OST : Trip-zone One-Shot Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
DCAEVT1 : Digital Comparator Output A Event 1 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
DCAEVT2 : Digital Comparator Output A Event 2 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
DCBEVT1 : Digital Comparator Output B Event 1 Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DCBEVT2 : Digital Comparator Output B Event 2 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Trip-Zone Flag Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT : Latched Trip Interrupt Status Flag
bits : 0 - 0 (1 bit)
access : read-only
CBC : Latched Status Flag for Cycle-By-Cycle Trip Event
bits : 1 - 1 (1 bit)
access : read-only
OST : Latched Status Flag for A One-Shot Trip Event
bits : 2 - 2 (1 bit)
access : read-only
DCAEVT1 : Latched Status Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-only
DCAEVT2 : Latched Status Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-only
DCBEVT1 : Latched Status Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-only
DCBEVT2 : Latched Status Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-only
Trip-Zone Clear Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Global Interrupt Clear Flag
bits : 0 - 0 (1 bit)
access : read-write
CBC : Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
bits : 1 - 1 (1 bit)
access : read-write
OST : Clear Flag for One-Shot Trip Latch
bits : 2 - 2 (1 bit)
access : read-write
DCAEVT1 : Clear Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-write
DCAEVT2 : Clear Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-write
DCBEVT1 : Clear Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-write
DCBEVT2 : Clear Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-write
Trip-Zone Force Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBC : Force a Cycle-by-Cycle Trip Event via Software
bits : 1 - 1 (1 bit)
access : read-write
OST : Force a One-Shot Trip Event via Software
bits : 2 - 2 (1 bit)
access : read-write
DCAEVT1 : Force Flag for Digital Compare Output A Event 1
bits : 3 - 3 (1 bit)
access : read-write
DCAEVT2 : Force Flag for Digital Compare Output A Event 2
bits : 4 - 4 (1 bit)
access : read-write
DCBEVT1 : Force Flag for Digital Compare Output B Event 1
bits : 5 - 5 (1 bit)
access : read-write
DCBEVT2 : Force Flag for Digital Compare Output B Event 2
bits : 6 - 6 (1 bit)
access : read-write
Event-Trigger Selection Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTESEL : ePWM Interrupt (EPWMx_INT) Selection Options
bits : 0 - 2 (3 bit)
access : read-write
INTEN : Enable ePWM Interrupt (EPWMx_INT) Generation
bits : 3 - 3 (1 bit)
access : read-write
SOCASEL : EPWMxSOCA Selection Options
bits : 8 - 10 (3 bit)
access : read-write
SOCAEN : Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
bits : 11 - 11 (1 bit)
access : read-write
SOCBSEL : EPWMxSOCB Selection Options
bits : 12 - 14 (3 bit)
access : read-write
SOCBEN : Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
bits : 15 - 15 (1 bit)
access : read-write
Event-Trigger Prescale Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPRD : ePWM Interrupt (EPWMx_INT) Period Select
bits : 0 - 1 (2 bit)
access : read-write
INTCNT : ePWM Interrupt Event (EPWMx_INT) Counter Register
bits : 2 - 3 (2 bit)
access : read-only
SOCAPRD : ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select
bits : 8 - 9 (2 bit)
access : read-write
SOCACNT : ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register
bits : 10 - 11 (2 bit)
access : read-only
SOCBPRD : ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select
bits : 12 - 13 (2 bit)
access : read-write
SOCBCNT : ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register
bits : 14 - 15 (2 bit)
access : read-only
Event-Trigger Flag Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT : Latched ePWM Interrupt (EPWMx_INT) Status Flag
bits : 0 - 0 (1 bit)
access : read-only
SOCA : Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
bits : 2 - 2 (1 bit)
access : read-only
SOCB : Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
bits : 3 - 3 (1 bit)
access : read-only
CTRDIR : PWM Counter Direction
bits : 31 - 31 (1 bit)
access : read-only
Event-Trigger Clear Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : ePWM Interrupt (EPWMx_INT) Flag Clear Bit
bits : 0 - 0 (1 bit)
access : read-write
SOCA : ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
bits : 2 - 2 (1 bit)
access : read-write
SOCB : ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit
bits : 3 - 3 (1 bit)
access : read-write
Event-Trigger Force Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : INT Force Bit
bits : 0 - 0 (1 bit)
access : read-write
SOCA : SOCA Force Bit
bits : 2 - 2 (1 bit)
access : read-write
SOCB : SOCB Force Bit
bits : 3 - 3 (1 bit)
access : read-write
PWM-Chopper Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPEN : PWM-chopping Enable
bits : 0 - 0 (1 bit)
access : read-write
OSHTWTH : One-Shot Pulse Width
bits : 1 - 4 (4 bit)
access : read-write
CHPFREQ : Chopping Clock Frequency
bits : 5 - 7 (3 bit)
access : read-write
CHPDUTY : Chopping Clock Duty Cycle
bits : 8 - 10 (3 bit)
access : read-write
CHPFREQ1 : Chopping Clock Frequency1
bits : 11 - 15 (5 bit)
access : read-write
Time Base Period register Mirror
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Compare Register A Mirror
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Time-Base Phase Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Digital Compare Trip Select
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCAHCOMPSEL : Digital Compare A High Input Select
bits : 0 - 3 (4 bit)
access : read-write
DCALCOMPSEL : Digital Compare A Low Input Select
bits : 4 - 7 (4 bit)
access : read-write
DCBHCOMPSEL : Digital Compare B High Input Select
bits : 8 - 11 (4 bit)
access : read-write
DCBLCOMPSEL : Digital Compare B Low Input Select
bits : 12 - 15 (4 bit)
access : read-write
Digital Compare A Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVT1SRCSEL : DCAEVT1 Source Signal Select
bits : 0 - 0 (1 bit)
access : read-write
EVT1FRCSYNCSEL : DCAEVT1 Force Synchronization Signal Select
bits : 1 - 1 (1 bit)
access : read-write
EVT1SOCE : DCAEVT1 SOC, Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write
EVT1SYNCE : DCAEVT1 SYNC, Enable/Disable
bits : 3 - 3 (1 bit)
access : read-write
EVT2SRCSEL : DCAEVT2 Source Signal Select
bits : 8 - 8 (1 bit)
access : read-write
EVT2FRCSYNCSEL : DCAEVT2 Force Synchronization Signal Select
bits : 9 - 9 (1 bit)
access : read-write
Digital Compare B Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVT1SRCSEL : DCBEVT1 Source Signal Select
bits : 0 - 0 (1 bit)
access : read-write
EVT1FRCSYNCSEL : DCBEVT1 Force Synchronization Signal Select
bits : 1 - 1 (1 bit)
access : read-write
EVT1SOCE : DCBEVT1 SOC, Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write
EVT1SYNCE : DCBEVT1 SYNC, Enable/Disable
bits : 3 - 3 (1 bit)
access : read-write
EVT2SRCSEL : DCBEVT2 Source Signal Select
bits : 8 - 8 (1 bit)
access : read-write
EVT2FRCSYNCSEL : DCBEVT2 Force Synchronization Signal Select
bits : 9 - 9 (1 bit)
access : read-write
Digital Compare Filter Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCSEL : Filter Block Signal Source Select
bits : 0 - 1 (2 bit)
access : read-write
BLANKE : Blanking Window Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write
BLANKINV : Blanking Window Inversion
bits : 3 - 3 (1 bit)
access : read-write
PULSESEL : Pulse Select For Blanking and Capture Alignment
bits : 4 - 5 (2 bit)
access : read-write
Digital Compare Capture Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPE : TBCTR Counter Capture Enable/Disable
bits : 0 - 0 (1 bit)
access : read-write
SHDWMODE : TBCTR Counter Capture Shadow Select Mode
bits : 1 - 1 (1 bit)
access : read-write
Digital Compare Filter Offset Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Digital Compare Filter Offset Counter Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Digital Compare Filter Window Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINDOW : Blanking Window Width
bits : 0 - 7 (8 bit)
access : read-write
Digital Compare Filter Window Counter Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WINDOWCNT : Blanking Window Counter
bits : 0 - 7 (8 bit)
access : read-only
Digital Compare Counter Capture Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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