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CMPSS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

COMPCTL

COMPDACCTL

DACHVALS

DACHVALA

RAMPMAXREFA

RAMPMAXREFS

RAMPDECVALA

RAMPDECVALS

COMPHYSCTL

RAMPSTS

DACLVALS

DACLVALA

RAMPDLYA

RAMPDLYS

CTRIPLFILCTL

CTRIPLFILCLKCTL

CTRIPHFILCTL

CTRIPHFILCLKCTL

COMPLOCK

DACBUFFEREN

DACTRIM

COMPSTS

COMPSTSCLR


COMPCTL

CMPSS Comparator Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPCTL COMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPHSOURCE COMPHINV CTRIPHSEL CTRIPOUTHSEL ASYNCHEN COMPLSOURCE COMPLINV CTRIPLSEL CTRIPOUTLSEL ASYNCLEN COMPDACE

COMPHSOURCE : High comparator input source
bits : 0 - 0 (1 bit)
access : read-write

COMPHINV : High comparator output invert
bits : 1 - 1 (1 bit)
access : read-write

CTRIPHSEL : High comparator CTRIPH source select
bits : 2 - 3 (2 bit)
access : read-write

CTRIPOUTHSEL : High comparator CTRIPOUTH source select
bits : 4 - 5 (2 bit)
access : read-write

ASYNCHEN : High comparator asynchronous path enable
bits : 6 - 6 (1 bit)
access : read-write

COMPLSOURCE : Low comparator input source
bits : 8 - 8 (1 bit)
access : read-write

COMPLINV : Low comparator output invert
bits : 9 - 9 (1 bit)
access : read-write

CTRIPLSEL : Low comparator CTRIPL source select
bits : 10 - 11 (2 bit)
access : read-write

CTRIPOUTLSEL : Low comparator CTRIPOUTL source select
bits : 12 - 13 (2 bit)
access : read-write

ASYNCLEN : Low comparator asynchronous path enable
bits : 14 - 14 (1 bit)
access : read-write

COMPDACE : Comparator/DAC enable
bits : 15 - 15 (1 bit)
access : read-write


COMPDACCTL

CMPSS DAC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPDACCTL COMPDACCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACSOURCE RAMPSOURCE SELREF_L RAMPLOADSEL SWLOADSEL SELREF_H DACL_PD COMPL_PD DACH_PD COMPH_PD FREESOFT

DACSOURCE : DAC source select
bits : 0 - 0 (1 bit)
access : read-write

RAMPSOURCE : Ramp generator source select
bits : 1 - 4 (4 bit)
access : read-write

SELREF_L : DACL reference select
bits : 5 - 5 (1 bit)
access : read-write

RAMPLOADSEL : Ramp load select
bits : 6 - 6 (1 bit)
access : read-write

SWLOADSEL : Software load select
bits : 7 - 7 (1 bit)
access : read-write

SELREF_H : DACH reference select
bits : 8 - 8 (1 bit)
access : read-write

DACL_PD : DACL Power Down
bits : 9 - 9 (1 bit)
access : read-write

COMPL_PD : COMPL Power Down
bits : 10 - 10 (1 bit)
access : read-write

DACH_PD : DACH Power Down
bits : 11 - 11 (1 bit)
access : read-write

COMPH_PD : COMPH Power Down
bits : 12 - 12 (1 bit)
access : read-write

FREESOFT : Free-run or software-run emulation behavior
bits : 14 - 15 (2 bit)
access : read-write


DACHVALS

CMPSS High DAC Value Shadow Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACHVALS DACHVALS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACVAL

DACVAL : High DAC shadow value
bits : 0 - 11 (12 bit)
access : read-write


DACHVALA

CMPSS High DAC Value Active Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DACHVALA DACHVALA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACVAL

DACVAL : High DAC active value
bits : 0 - 11 (12 bit)
access : read-only


RAMPMAXREFA

CMPSS Ramp Max Reference Active Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMPMAXREFA RAMPMAXREFA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RAMPMAXREFS

CMPSS Ramp Max Reference Shadow Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMPMAXREFS RAMPMAXREFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RAMPDECVALA

CMPSS Ramp Decrement Value Active Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMPDECVALA RAMPDECVALA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RAMPDECVALS

CMPSS Ramp Decrement Value Shadow Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMPDECVALS RAMPDECVALS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COMPHYSCTL

CMPSS Comparator Hysteresis Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPHYSCTL COMPHYSCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HYS_L HYS_L_EN HYS_H HYS_H_EN

HYS_L : Low comparator hysteresis
bits : 0 - 1 (2 bit)
access : read-write

HYS_L_EN : Low comparator hysteresis enable
bits : 2 - 2 (1 bit)
access : read-write

HYS_H : High comparator hysteresis
bits : 3 - 4 (2 bit)
access : read-write

HYS_H_EN : High comparator hysteresis enable
bits : 5 - 5 (1 bit)
access : read-write


RAMPSTS

CMPSS Ramp Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMPSTS RAMPSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DACLVALS

CMPSS Low DAC Value Shadow Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACLVALS DACLVALS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACVAL

DACVAL : Low DAC shadow value
bits : 0 - 11 (12 bit)
access : read-write


DACLVALA

CMPSS Low DAC Value Active Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DACLVALA DACLVALA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACVAL

DACVAL : High DAC active value
bits : 0 - 11 (12 bit)
access : read-only


RAMPDLYA

CMPSS Ramp Delay Active Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMPDLYA RAMPDLYA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELAY

DELAY : Ramp delay active value
bits : 0 - 12 (13 bit)
access : read-only


RAMPDLYS

CMPSS Ramp Delay Shadow Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMPDLYS RAMPDLYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELAY

DELAY : Ramp delay shadow value
bits : 0 - 12 (13 bit)
access : read-write


CTRIPLFILCTL

CTRIPL Filter Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRIPLFILCTL CTRIPLFILCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPWIN THRESH FILINIT

SAMPWIN : Low filter sample window size
bits : 4 - 8 (5 bit)
access : read-write

THRESH : Low filter majority voting threshold
bits : 9 - 13 (5 bit)
access : read-write

FILINIT : Low filter initialization
bits : 15 - 15 (1 bit)
access : read-write


CTRIPLFILCLKCTL

CTRIPL Filter Clock Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRIPLFILCLKCTL CTRIPLFILCLKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPRESCALE

CLKPRESCALE : Low filter sample clock prescale
bits : 0 - 9 (10 bit)
access : read-write


CTRIPHFILCTL

CTRIPH Filter Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRIPHFILCTL CTRIPHFILCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPWIN THRESH FILINIT

SAMPWIN : High filter sample window size
bits : 4 - 8 (5 bit)
access : read-write

THRESH : High filter majority voting threshold
bits : 9 - 13 (5 bit)
access : read-write

FILINIT : High filter initialization
bits : 15 - 15 (1 bit)
access : read-write


CTRIPHFILCLKCTL

CTRIPH Filter Clock Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRIPHFILCLKCTL CTRIPHFILCLKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPRESCALE

CLKPRESCALE : High filter sample clock prescale
bits : 0 - 9 (10 bit)
access : read-write


COMPLOCK

CMPSS Lock Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPLOCK COMPLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPCTL COMPHYSCTL DACCTL CTRIP

COMPCTL : Lock write-access to the COMPCTL register
bits : 0 - 0 (1 bit)
access : read-write

COMPHYSCTL : Lock write-access to the COMPHYSCTL register
bits : 1 - 1 (1 bit)
access : read-write

DACCTL : Lock write-access to the DACCTL register
bits : 2 - 2 (1 bit)
access : read-write

CTRIP : Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers
bits : 3 - 3 (1 bit)
access : read-write


DACBUFFEREN

DAC Output Enable Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACBUFFEREN DACBUFFEREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACOUTEN

DACOUTEN : DAC output enable
bits : 0 - 0 (1 bit)
access : read-write


DACTRIM

DAC Trim Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACTRIM DACTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET_TRIM_L OFFSET_TRIM_H

OFFSET_TRIM_L : DACL Offset Trim
bits : 0 - 7 (8 bit)
access : read-write

OFFSET_TRIM_H : DACH Offset Trim
bits : 8 - 15 (8 bit)
access : read-write


COMPSTS

CMPSS Comparator Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPSTS COMPSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPHSTS COMPHLATCH COMPLSTS COMPLLATCH

COMPHSTS : High comparator digital filter output
bits : 0 - 0 (1 bit)
access : read-only

COMPHLATCH : Latched value of high comparator digital filter output
bits : 1 - 1 (1 bit)
access : read-only

COMPLSTS : Low comparator digital filter output
bits : 8 - 8 (1 bit)
access : read-only

COMPLLATCH : Latched value of low comparator digital filter output
bits : 9 - 9 (1 bit)
access : read-only


COMPSTSCLR

CMPSS Comparator Status Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPSTSCLR COMPSTSCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLATCHCLR HSYNCCLREN LLATCHCLR LSYNCCLREN

HLATCHCLR : High comparator latch software clear
bits : 1 - 1 (1 bit)
access : read-write

HSYNCCLREN : High comparator latch PWMSYNC clear
bits : 2 - 2 (1 bit)
access : read-write

LLATCHCLR : Low comparator latch software clear
bits : 9 - 9 (1 bit)
access : read-write

LSYNCCLREN : Low comparator latch PWMSYNC clear
bits : 10 - 10 (1 bit)
access : read-write



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