\n

SYSREG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD00 byte (0x0)
mem_usage : registers
protection :

Registers

PWM_CFG

SYSINT_STATUS

SYSRAM_STATUS

CHIP_ID

ETIMER_CFG

SYSTICK_CFG

SYSRAM_CTRL

RXEV_CTRL

ACCESS_EN

MISC_CTRL

VERSION


PWM_CFG

PWM confige Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CFG PWM_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYSINT_STATUS

SYSINT status Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSINT_STATUS SYSINT_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ppu_intr eflash_intr sysram0_intr sysram0 sysram1_intr sysram1 div_intr mac_intr cordic_intr pwm0_intr pwm1_intr pwm2_intr pwm4_intr pwm0tz_intr pwm1tz_intr pwm2tz_intr pwm4tz_intr

ppu_intr : ppu_intr
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

eflash_intr : eflash_intr
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

sysram0_intr : sysram0_intr
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

sysram0 : sysram0
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

sysram1_intr : sysram1_intr
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

sysram1 : sysram1
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

div_intr : div_intr
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

mac_intr : mac_intr
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

cordic_intr : cordic_intr
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm0_intr : pwm0_intr
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm1_intr : pwm1_intr
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm2_intr : pwm2_intr
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm4_intr : pwm4_intr
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm0tz_intr : pwm0tz_intr
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm1tz_intr : pwm1tz_intr
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm2tz_intr : pwm2tz_intr
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pwm4tz_intr : pwm4tz_intr
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.


SYSRAM_STATUS

SYSRAM status Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSRAM_STATUS SYSRAM_STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CHIP_ID

CHIP_ID Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID CHIP_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETIMER_CFG

ETIMER confige Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETIMER_CFG ETIMER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYSTICK_CFG

SYSTICK confige Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTICK_CFG SYSTICK_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYSRAM_CTRL

RAM control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSRAM_CTRL SYSRAM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sysram0_parity_intren sysram0_parity_err_clr sysram1_parity_intren sysram1_parity_err_clr sysram0_ms sysram0_mse sysram1_ms sysram1_mse

sysram0_parity_intren : sysram0_parity_intren
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram0_parity_err_clr : sysram0_parity_err_clr
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram1_parity_intren : sysram1_parity_intren
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram1_parity_err_clr : sysram1_parity_err_clr
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram0_ms : sysram0_ms
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram0_mse : sysram0_mse
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram1_ms : sysram1_ms
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysram1_mse : sysram1_mse
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


RXEV_CTRL

RXEV control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXEV_CTRL RXEV_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ACCESS_EN

ACCESS ENABLE Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACCESS_EN ACCESS_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MISC_CTRL

MISC control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC_CTRL MISC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VERSION

VERSION Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.