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WCO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :

Registers

CONFIG

STATUS

DPLL

TRIM


CONFIG

WCO Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_EN LPM_AUTO EXT_INPUT_EN ENBUS DPLL_ENABLE IP_ENABLE

LPM_EN : Force block into Low Power Mode: 0: Do not force low power mode (LPM) on 1: Force low power mode (LPM) on
bits : 0 - 0 (1 bit)
access : read-write

LPM_AUTO : Automatically control low power mode (only relevant when LPM_EN=0): 0: Do not enter low power mode (LPM) in DeepSleep 1: Enter low power mode (LPM) in DeepSleep. The logic monitors !act_power_en to determine the device has entered DeepSleep.
bits : 1 - 2 (2 bit)
access : read-write

EXT_INPUT_EN : Disables the load resistor and allows external clock input for pad_xin
bits : 2 - 4 (3 bit)
access : read-write

ENBUS : Test Mode Control bits enbus[7] - N/A enbus[6] - 1=enable both primary Beta Multipliers enbus[5] - N/A enbus[4] - N/A enbus[3] - Load Resistor Control enbus[2] - Load Resistor Control enbus[1] - Load Resistor Control enbus[0] - Load Resistor Control
bits : 16 - 39 (24 bit)
access : read-write

DPLL_ENABLE : Enable DPLL operation. The Oscillator is specified to be stable after 500 ms thus the DPLL should be asserted no sooner than that after IP_ENABLE is set.
bits : 30 - 60 (31 bit)
access : read-write

IP_ENABLE : Master enable for IP - disables both WCO and DPLL
bits : 31 - 62 (32 bit)
access : read-write


STATUS

WCO Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_BLNK_A

OUT_BLNK_A : Indicates that output has transitioned - This bit is intended for Test Mode Only and is not a reliable indicator.
bits : 0 - 0 (1 bit)
access : read-only


DPLL

WCO DPLL Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLL DPLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DPLL_MULT DPLL_LF_IGAIN DPLL_LF_PGAIN DPLL_LF_LIMIT

DPLL_MULT : Multiplier to determine IMO frequency in multiples of the WCO frequency Fimo = (DPLL_MULT + 1) * Fwco
bits : 0 - 10 (11 bit)
access : read-write

DPLL_LF_IGAIN : DPLL Loop Filter Integral Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0
bits : 16 - 34 (19 bit)
access : read-write

DPLL_LF_PGAIN : DPLL Loop Filter Proportionial Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0
bits : 19 - 40 (22 bit)
access : read-write

DPLL_LF_LIMIT : Maximum IMO offset allowed (used to prevent DPLL dynamics from selecting an IMO frequency that the logic cannot support)
bits : 22 - 51 (30 bit)
access : read-write


TRIM

WCO Trim Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XGM LPM_GM XGM_FOR_LPM_AUTO LPM_GM_FOR_LPM_AUTO

XGM : Amplifier GM setting - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode. 0x0 - 3370 nA 0x1 - 2620 nA 0x2 - 2250 nA 0x3 - 1500 nA 0x4 - 1870 nA 0x5 - 1120 nA 0x6 - 750 nA 0x7 - 0 nA
bits : 0 - 2 (3 bit)
access : read-write

LPM_GM : GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode.
bits : 4 - 9 (6 bit)
access : read-write

XGM_FOR_LPM_AUTO : Amplifier GM setting - Used when WCO.LPM_AUTO=1 and in DeepSleep mode 0x0 - 3370 nA 0x1 - 2620 nA 0x2 - 2250 nA 0x3 - 1500 nA 0x4 - 1870 nA 0x5 - 1120 nA 0x6 - 750 nA 0x7 - 0 nA
bits : 8 - 18 (11 bit)
access : read-write

LPM_GM_FOR_LPM_AUTO : GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=1 and in DeepSleep mode
bits : 12 - 25 (14 bit)
access : read-write



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