PWR_CONTROL

TST_MODE

CLK_SELECT

CLK_ILO_CONFIG

CLK_IMO_CONFIG

CLK_DFT_SELECT

WDT_DISABLE_KEY

WDT_COUNTER

PWR_KEY_DELAY

WDT_MATCH

SRSS_INTR

SRSS_INTR_SET

SRSS_INTR_MASK

RES_CAUSE

PWR_DDFT_SELECT

PWR_BG_TRIM1

PWR_BG_TRIM2

CLK_IMO_SELECT

CLK_IMO_TRIM1

CLK_IMO_TRIM2

PWR_PWRSYS_TRIM1

CLK_IMO_TRIM3

POWER_MODE : Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DEBUG_SESSION : Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)
bits : 4 - 8 (5 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LPM_READY : Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode. 0: If DEEPSLEEP mode is requested, device will enter SLEEP mode. When low power regulators are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP works as described.
bits : 5 - 10 (6 bit)
access : read-only

OVER_TEMP_EN : Enables the die over temperature sensor. Must be enabled when using the TEMP_HIGH interrupt.
bits : 16 - 32 (17 bit)
access : read-write

OVER_TEMP_THRESH : Over-temperature threshold. 0: TEMP_HIGH condition occurs between 120C and 125C. 1: TEMP_HIGH condition occurs between 60C and 75C (used for testing).
bits : 17 - 34 (18 bit)
access : read-write

SPARE : Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion. Engineering only.
bits : 18 - 37 (20 bit)
access : read-only

EXT_VCCD : Always write 0 except as noted below. PSoC4-S0 and Streetfighter CapSense products may set this bit if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (BOD) unless both Vddd and Vccd pins are supplied externally. This register bit only resets for XRES, POR, or a detected BOD.
bits : 23 - 46 (24 bit)
access : read-write

SWD_CONNECTED : 0: SWD not active 1: SWD activated (Line Reset and Connect sequence passed) (Note: this bit replaces TST_CTRL.SWD_CONNECTED and is present in all M0S8 products except TSG4)
bits : 2 - 4 (3 bit)
access : read-only

BLOCK_ALT_XRES : Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test. When set, this bit blocks the alternate XRES function, such that the pin can be used for normal I/O or for ddft/adft observation. See SAS Part-V and Part-IX for details. This register bit only resets for XRES, POR, or a detected BOD.
bits : 28 - 56 (29 bit)
access : read-write

TEST_KEY_DFT_EN : This bit is set when a XRES test mode key is shifted in. It is the value of the test_key_dft_en signal. When this bit is set, the BootROM will not yield execution to the FLASH image (same function as setting TEST_MODE bit below).
bits : 30 - 60 (31 bit)
access : read-only

TEST_MODE : 0: Normal operation mode 1: Test mode (any test mode) Setting this bit will prevent BootROM from yielding execution to Flash image.
bits : 31 - 62 (32 bit)
access : read-write

HFCLK_SEL : Selects a source for clk_hf and dsi_in[0]. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HFCLK_DIV : Selects clk_hf predivider value.
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUMP_SEL : Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings.
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSCLK_DIV : Select clk_sys prescaler value.
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENABLE : Master enable for ILO oscillator. This bit is hardware set whenever the WD_DISABLE_KEY is not set to the magic value.
bits : 31 - 62 (32 bit)
access : read-write

ENABLE : Master enable for IMO oscillator. Clearing this bit will disable the IMO. Don't do this if the system is running off it.
bits : 31 - 62 (32 bit)
access : read-write

DFT_SEL0 : Select signal for DFT output #0
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFT_DIV0 : DFT Output Divide Down.
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFT_EDGE0 : Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0).
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFT_SEL1 : Select signal for DFT output #1
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFT_DIV1 : DFT Output Divide Down.
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFT_EDGE1 : Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0).
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEY : Disables WDT reset when equal to 0xACED8865. The WDT reset functions normally for any other setting.
bits : 0 - 31 (32 bit)
access : read-write

COUNTER : Current value of WDT Counter
bits : 0 - 15 (16 bit)
access : read-only

WAKEUP_HOLDOFF : Delay to wait for references to settle on wakeup from deepsleep. BOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded. The default assumes the output of the predivider is 48MHz + 3 percent. Firmware may scale this setting according to the fastest actual clock frequency that can occur when waking from DEEPSLEEP.
bits : 0 - 9 (10 bit)
access : read-write

MATCH : Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match).
bits : 0 - 15 (16 bit)
access : read-write

IGNORE_BITS : The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Note that certain products may enforce a minimum value for this register through design time configuration.
bits : 16 - 35 (20 bit)
access : read-write

WDT_MATCH : WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. Clearing this bit also feeds the watch dog. Missing 2 interrupts in a row will generate brown-out reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.
bits : 0 - 0 (1 bit)
access : read-write

TEMP_HIGH : Regulator over-temp interrupt. This interrupt can occur when a short circuit exists on the vccd pin or when extreme loads are applied on IO-cells causing the die to overheat. Firmware is encourage to shutdown all IO cells and then go to DeepSleep mode when this interrupt occurs if protection against such conditions is desired.
bits : 1 - 2 (2 bit)
access : read-write

TEMP_HIGH : Writing 1 to this bit internally sets the overtemp interrupt. This can be observed by reading SRSS_INTR.TEMP_HIGH. This bit always reads back as zero.
bits : 1 - 2 (2 bit)
access : read-write

WDT_MATCH : Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts.
bits : 0 - 0 (1 bit)
access : read-write

TEMP_HIGH : Masks REG_OVERTEMP interrupt
bits : 1 - 2 (2 bit)
access : read-write

RESET_WDT : A WatchDog Timer reset has occurred since last power cycle.
bits : 0 - 0 (1 bit)
access : read-write

RESET_PROT_FAULT : A protection violation occurred that requires a RESET. This includes, but is not limited to, hitting a debug breakpoint while in Privileged Mode.
bits : 3 - 6 (4 bit)
access : read-write

RESET_SOFT : Cortex-M0 requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware.
bits : 4 - 8 (5 bit)
access : read-write

DDFT0_SEL : Select signal for power DDFT output #0
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DDFT1_SEL : Select signal for power DDFT output #1
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REF_VTRIM : Trims the bandgap reference voltage output. Used to trim the VBG to the voltage where its temperature curvature is minimal. Bit [5] is unused within the bandgap block.
bits : 0 - 5 (6 bit)
access : read-write

REF_ITRIM : Trims the bandgap reference current output. Used to trim the IBG to the voltage where its temperature curvature is minimal.
bits : 0 - 5 (6 bit)
access : read-write

FREQ : Select operating frequency
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OFFSET : Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting (IMO_TRIM2) and stored in SFLASH. This field is hardware updated during USB osclock mode. This field is mapped to the most significant bits of the IMO trim imo_clk_trim[10:3]. The step size of 1 LSB on this field is approximately 120 kHz.
bits : 0 - 7 (8 bit)
access : read-write

FSOFFSET : Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is hardware updated during USB osclock mode. This field is mapped to the least significant bits of the IMO trim imo_clk_trim[2:0]. The step size of 1 LSB on this field is approximately 15 kHz.
bits : 0 - 2 (3 bit)
access : read-write

DPSLP_REF_TRIM : Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator.
bits : 0 - 3 (4 bit)
access : read-write

SPARE_TRIM : Active-Reference temperature compensation trim (repurposed from spare bits). Bits [7:6] - trim the Active-Reference IREF temperature coefficient (TC). 00: TC = 0 (unchanged) 01: TC = +80ppm/C 10: TC = -80ppm/C 11: TC = -150ppm/C Bits [5:4] - trim the Active-Reference VREF temperature coefficient (TC). 00: TC = 0 (unchanged) 01: TC = -50ppm/C 10: TC = -80ppm/C 11: TC = +150ppm/C
bits : 4 - 11 (8 bit)
access : read-write

STEPSIZE : IMO trim stepsize bits. These bits are determined at manufacturing time to adjust for process variation. They are used to tune the stepsize of the FSOFFSET and OFFSET trims.
bits : 0 - 4 (5 bit)
access : read-write

TCTRIM : IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the Cypress provided frequency change algorithm.
bits : 5 - 11 (7 bit)
access : read-write