\n
address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection :
Port output data register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : IO pad 0 output data.
bits : 0 - 0 (1 bit)
access : read-write
DATA1 : IO pad 1 output data.
bits : 1 - 2 (2 bit)
access : read-write
DATA2 : IO pad 2 output data.
bits : 2 - 4 (3 bit)
access : read-write
DATA3 : IO pad 3 output data.
bits : 3 - 6 (4 bit)
access : read-write
DATA4 : IO pad 4 output data.
bits : 4 - 8 (5 bit)
access : read-write
DATA5 : IO pad 5 output data.
bits : 5 - 10 (6 bit)
access : read-write
DATA6 : IO pad 6 output data.
bits : 6 - 12 (7 bit)
access : read-write
DATA7 : IO pad 7 output data.
bits : 7 - 14 (8 bit)
access : read-write
Port interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Interrupt pending on IO pad 0. Firmware writes 1 to clear the interrupt.
bits : 0 - 0 (1 bit)
access : read-write
DATA1 : Interrupt pending on IO pad 1. Firmware writes 1 to clear the interrupt.
bits : 1 - 2 (2 bit)
access : read-write
DATA2 : Interrupt pending on IO pad 2. Firmware writes 1 to clear the interrupt.
bits : 2 - 4 (3 bit)
access : read-write
DATA3 : Interrupt pending on IO pad 3. Firmware writes 1 to clear the interrupt.
bits : 3 - 6 (4 bit)
access : read-write
DATA4 : Interrupt pending on IO pad 4. Firmware writes 1 to clear the interrupt.
bits : 4 - 8 (5 bit)
access : read-write
DATA5 : Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt.
bits : 5 - 10 (6 bit)
access : read-write
DATA6 : Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt.
bits : 6 - 12 (7 bit)
access : read-write
DATA7 : Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt.
bits : 7 - 14 (8 bit)
access : read-write
FLT_DATA : Deglitched interrupt pending (selected by FLT_SELECT).
bits : 8 - 16 (9 bit)
access : read-write
PS_DATA0 : `
bits : 16 - 32 (17 bit)
access : read-only
PS_DATA1 : N/A
bits : 17 - 34 (18 bit)
access : read-only
PS_DATA2 : N/A
bits : 18 - 36 (19 bit)
access : read-only
PS_DATA3 : N/A
bits : 19 - 38 (20 bit)
access : read-only
PS_DATA4 : N/A
bits : 20 - 40 (21 bit)
access : read-only
PS_DATA5 : N/A
bits : 21 - 42 (22 bit)
access : read-only
PS_DATA6 : N/A
bits : 22 - 44 (23 bit)
access : read-only
PS_DATA7 : N/A
bits : 23 - 46 (24 bit)
access : read-only
PS_FLT_DATA : This is a duplicate of the contents of the PS register, provided here to allow reading of both pin state and interrupt state of the port in a single read operation.
bits : 24 - 48 (25 bit)
access : read-only
Interrupt port cause register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PORT_INT : Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a shared/combined interrupt line 'gpio_interrupt'. The SW ISR reads the register to deternine which IO port(s) is responsible for the shared/combined interrupt line 'gpio_interrupt'. Once, the IO port(s) is determined, the IO port's INTR register is read to determine the IO pad(s) in the IO port that caused the interrupt.
bits : 0 - 31 (32 bit)
access : read-only
GPIOV1P2 Detect output
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DET : Indicates HI when VDDIO is in 1.8V range, and LOW when VDDIO is in 1.2V range.
bits : 0 - 0 (1 bit)
access : read-only
Port SIO configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAIR_VREG01_EN : Selects output buffer mode: 0: unregulated output buffer 1: regulated output buffer
bits : 0 - 0 (1 bit)
access : read-write
PAIR_IBUF01_SEL : Selects input buffer mode: 0: singled ended input buffer 1: differential input buffer
bits : 1 - 2 (2 bit)
access : read-write
PAIR_VTRIP01_SEL : Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1') '0': trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) Please refer to s8iom0s8 BROS 001-70428, section 4.2.7 for more details.
bits : 2 - 4 (3 bit)
access : read-write
PAIR_VREF01_SEL : Selects reference voltage Vref for trip-point of input buffer: 0: trip-point reference of SRSS internal referece Vref (1.2V) 1: trip-point reference of SRSS internal referece Vref (1.2V) 2: trip-point reference of AMUXBUS_A 3: trip-point reference of AMUXBUS_B Please refer to s8iom0s8 BROS 001-70428, section 4.2.7 for more details.
bits : 3 - 7 (5 bit)
access : read-write
PAIR_VOH01_SEL : Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). 0: Voh = 1*reference e.g. reference at 1.2V -> Voh = 1.2V 1: Voh = 1.25*reference e.g. reference at 1.2V -> Voh = 1.5V 2: Voh = 1.49*reference e.g. reference at 1.2V -> Voh = ~1.8V 3: Voh = 1.67*reference e.g. reference at 1.2V -> Voh = 2V 4: Voh = 2.08*reference e.g. reference at 1.2V -> Voh = 2.5V 5: Voh = 2.5*reference e.g. reference at 1.2V -> Voh = 3V 6: Voh = 2.78*reference e.g. reference at 1.2V -> Voh = ~3.3V 7: Voh = 4.16*reference e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on VOH is limited to Vddio - 400mV
bits : 5 - 12 (8 bit)
access : read-write
PAIR_VREG23_EN : See corresponding definition for IO pads 2 and 3.
bits : 8 - 16 (9 bit)
access : read-write
PAIR_IBUF23_SEL : See corresponding definition for IO pads 2 and 3.
bits : 9 - 18 (10 bit)
access : read-write
PAIR_VTRIP23_SEL : See corresponding definition for IO pads 2 and 3.
bits : 10 - 20 (11 bit)
access : read-write
PAIR_VREF23_SEL : See corresponding definition for IO pads 2 and 3.
bits : 11 - 23 (13 bit)
access : read-write
PAIR_VOH23_SEL : See corresponding definition for IO pads 2 and 3.
bits : 13 - 28 (16 bit)
access : read-write
PAIR_VREG45_EN : See corresponding definition for IO pads 4 and 5.
bits : 16 - 32 (17 bit)
access : read-write
PAIR_IBUF45_SEL : See corresponding definition for IO pads 4 and 5.
bits : 17 - 34 (18 bit)
access : read-write
PAIR_VTRIP45_SEL : See corresponding definition for IO pads 4 and 5.
bits : 18 - 36 (19 bit)
access : read-write
PAIR_VREF45_SEL : See corresponding definition for IO pads 4 and 5.
bits : 19 - 39 (21 bit)
access : read-write
PAIR_VOH45_SEL : See corresponding definition for IO pads 4 and 5.
bits : 21 - 44 (24 bit)
access : read-write
PAIR_VREG67_EN : See corresponding definition for IO pads 6 and 7.
bits : 24 - 48 (25 bit)
access : read-write
PAIR_IBUF67_SEL : See corresponding definition for IO pads 6 and 7.
bits : 25 - 50 (26 bit)
access : read-write
PAIR_VTRIP67_SEL : See corresponding definition for IO pads 6 and 7.
bits : 26 - 52 (27 bit)
access : read-write
PAIR_VREF67_SEL : See corresponding definition for IO pads 6 and 7.
bits : 27 - 55 (29 bit)
access : read-write
PAIR_VOH67_SEL : See corresponding definition for IO pads 6 and 7.
bits : 29 - 60 (32 bit)
access : read-write
Port configuration register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_DIS0 : Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver.
bits : 0 - 0 (1 bit)
access : read-write
INP_DIS1 : Disables the input buffer for IO pad 1.
bits : 1 - 2 (2 bit)
access : read-write
INP_DIS2 : Disables the input buffer for IO pad 2.
bits : 2 - 4 (3 bit)
access : read-write
INP_DIS3 : Disables the input buffer for IO pad 3.
bits : 3 - 6 (4 bit)
access : read-write
INP_DIS4 : Disables the input buffer for IO pad 4.
bits : 4 - 8 (5 bit)
access : read-write
INP_DIS5 : Disables the input buffer for IO pad 5.
bits : 5 - 10 (6 bit)
access : read-write
INP_DIS6 : Disables the input buffer for IO pad 6.
bits : 6 - 12 (7 bit)
access : read-write
INP_DIS7 : Disables the input buffer for IO pad 7.
bits : 7 - 14 (8 bit)
access : read-write
Port IO pad state register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA0 : IO pad 0 state: 1: Logic high, if the pin voltage is above the input buffer threshold, logic high. 0: Logic low, if the pin voltage is below that threshold, logic low. If the drive mode for the pin is set to high Z Analog, the pin state will read 0 independent of the voltage on the pin.
bits : 0 - 0 (1 bit)
access : read-only
DATA1 : IO pad 1 state.
bits : 1 - 2 (2 bit)
access : read-only
DATA2 : IO pad 2 state.
bits : 2 - 4 (3 bit)
access : read-only
DATA3 : IO pad 3 state.
bits : 3 - 6 (4 bit)
access : read-only
DATA4 : IO pad 4 state.
bits : 4 - 8 (5 bit)
access : read-only
DATA5 : IO pad 5 state.
bits : 5 - 10 (6 bit)
access : read-only
DATA6 : IO pad 6 state.
bits : 6 - 12 (7 bit)
access : read-only
DATA7 : IO pad 7 state.
bits : 7 - 14 (8 bit)
access : read-only
FLT_DATA : Reads of this register return the logical state of the filtered pin.
bits : 8 - 16 (9 bit)
access : read-only
Port output data set register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] set to '1'.
bits : 0 - 7 (8 bit)
access : read-write
Port output data clear register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] set to '0'.
bits : 0 - 7 (8 bit)
access : read-write
Port output data invert register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] inverted ('0' => '1', '1' => '0').
bits : 0 - 7 (8 bit)
access : read-write
Port drive strength register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DS0 : The GPIO drive strength for IO pad 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
Refer to s8iom0s8v1p2 BROS Table11.
1 : 1
Refer to s8iom0s8v1p2 BROS Table11.
2 : 2
Refer to s8iom0s8v1p2 BROS Table11.
3 : 3
Refer to s8iom0s8v1p2 BROS Table11.
End of enumeration elements list.
DS1 : The GPIO drive strength for IO pad 1.
bits : 2 - 5 (4 bit)
access : read-write
DS2 : The GPIO drive strength for IO pad 2.
bits : 4 - 9 (6 bit)
access : read-write
DS3 : The GPIO drive strength for IO pad 3.
bits : 6 - 13 (8 bit)
access : read-write
DS4 : The GPIO drive strength for IO pad 4.
bits : 8 - 17 (10 bit)
access : read-write
DS5 : The GPIO drive strength for IO pad 5.
bits : 10 - 21 (12 bit)
access : read-write
DS6 : The GPIO drive strength for IO pad 6.
bits : 12 - 25 (14 bit)
access : read-write
DS7 : The GPIO drive strength for IO pad 7.
bits : 14 - 29 (16 bit)
access : read-write
PORT_V1P2_VTRIP_SEL : For GPIOV1P2: 0: 1.2V VDDIO 1: 1.8V VDDIO For GPIOV1P_I2C cells: Used in conjunction with PORT_V1P2_IB_MODE_SEL PORT_V1P2_VTRIP_SEL,PORT_V1P2_IB_MODE_SEL 0,0 - VDDIO 1.2V and VDDI2C 1.2V 1,1 - VDDIO 1.2V and VDDI2C 1.8V 0,0 - VDDIO 1.8V and VDDI2C 1.8V All other combinations are illegal
bits : 16 - 32 (17 bit)
access : read-write
PORT_V1P2_IB_MODE_SEL : For GPIOV1P2 cell, 0: vtrip_sel register controls the vtrip_sel of the IO cells 1: vddio detect cell output controls the vtrip_sel of the IO cells For GPIOV1P2_I2C cells, refer to PORT_VTRIP_SEL description for usage.
bits : 17 - 34 (18 bit)
access : read-write
IO filter config register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM0 : trim bits for 50ns filter on IO pad 0
bits : 0 - 1 (2 bit)
access : read-write
TRIM1 : trim bits for 50ns filter on IO pad 1
bits : 2 - 5 (4 bit)
access : read-write
TRIM2 : trim bits for 50ns filter on IO pad 2
bits : 4 - 9 (6 bit)
access : read-write
TRIM3 : trim bits for 50ns filter on IO pad 3
bits : 6 - 13 (8 bit)
access : read-write
TRIM4 : trim bits for 50ns filter on IO pad 4
bits : 8 - 17 (10 bit)
access : read-write
TRIM5 : trim bits for 50ns filter on IO pad 5
bits : 10 - 21 (12 bit)
access : read-write
TRIM6 : trim bits for 50ns filter on IO pad 6
bits : 12 - 25 (14 bit)
access : read-write
TRIM7 : trim bits for 50ns filter on IO pad 7
bits : 14 - 29 (16 bit)
access : read-write
FILT0_EN : Filter selection for IO pad 0
bits : 16 - 32 (17 bit)
access : read-write
FILT1_EN : Filter selection for IO pad 1
bits : 17 - 34 (18 bit)
access : read-write
FILT2_EN : Filter selection for IO pad 2
bits : 18 - 36 (19 bit)
access : read-write
FILT3_EN : Filter selection for IO pad 3
bits : 19 - 38 (20 bit)
access : read-write
FILT4_EN : Filter selection for IO pad 4
bits : 20 - 40 (21 bit)
access : read-write
FILT5_EN : Filter selection for IO pad 5
bits : 21 - 42 (22 bit)
access : read-write
FILT6_EN : Filter selection for IO pad 6
bits : 22 - 44 (23 bit)
access : read-write
FILT7_EN : Filter selection for IO pad 7
bits : 23 - 46 (24 bit)
access : read-write
Port configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DM0 : The GPIO drive mode for IO pad 0. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : OFF
Mode 0 (analog mode): Output buffer off (high Z). Input buffer off.
1 : INPUT
Mode 1: Output buffer off (high Z). Input buffer on.
2 : 0_PU
Mode 2: Strong pull down ('0'), weak/resistive pull up (PU). Input buffer on. For GPIOV1P2_I2C, Strong pull down only.
3 : PD_1
Mode 3: Weak/resistive pull down (PD), strong pull up ('1'). Input buffer on. For GPIOV1P2_I2C: Weak pull down only.
4 : 0_Z
Mode 4: Strong pull down ('0'), open drain (pull up off). Input buffer on. For GPIOV1P2_I2C, Strong pull down only.
5 : Z_1
Mode 5: Open drain (pull down off), strong pull up ('1'). Input buffer on. Illegal for GPIOV1P2_I2C
6 : 0_1
Mode 6: Strong pull down ('0'), strong pull up ('1'). Input buffer on. For GPIOV1P2_I2C, Strong pull down only.
7 : PD_PU
Mode 7: Weak/resistive pull down (PD), weak/resistive pull up (PU). Input buffer on. For GPIOV1P2_I2C: Weak pull down only.
End of enumeration elements list.
DM1 : The GPIO drive mode for IO pad 1.
bits : 3 - 8 (6 bit)
access : read-write
DM2 : The GPIO drive mode for IO pad 2.
bits : 6 - 14 (9 bit)
access : read-write
DM3 : The GPIO drive mode for IO pad 3.
bits : 9 - 20 (12 bit)
access : read-write
DM4 : The GPIO drive mode for IO pad 4.
bits : 12 - 26 (15 bit)
access : read-write
DM5 : The GPIO drive mode for IO pad 5.
bits : 15 - 32 (18 bit)
access : read-write
DM6 : The GPIO drive mode for IO pad 6.
bits : 18 - 38 (21 bit)
access : read-write
DM7 : The GPIO drive mode for IO pad 7.
bits : 21 - 44 (24 bit)
access : read-write
PORT_VTRIP_SEL : The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage. Note: this bit is ignored for SIO ports, the VTRIP_SEL settings in the SIO register are used instead (a separate VTRIP_SEL is provided for each pin pair). 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. For GPIOV1P2 and GPIOV1P_I2C cells, PC.PORT_VTRIP_SEL is unused. Refer to DS register
bits : 24 - 48 (25 bit)
access : read-write
PORT_SLOW : This field controls the output edge rate of all pins on the port: '0': fast. '1': slow.
bits : 25 - 50 (26 bit)
access : read-write
PORT_HYST_TRIM : This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer. The voltage reference comes from the VREFGEN block and is only available when using the VREFGEN block: '0': <= 2.2 V input signaling Voltage. '1': > 2.2 V input signaling Voltage.
bits : 27 - 54 (28 bit)
access : read-write
PORT_SLEW_CTL : Slew control. Only used in the O_Z drive mode (mode 4: strong pull down, open drain): This field is intended for I2C functionality. See BROS 001-70428 for more details.
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
0 : PORT_SLEW_CTL_0
HS mode (100pf < Cb < 400pF, 1.71
1 : PORT_SLEW_CTL_1
HS mode (Cb<100pf,1.71
2 : PORT_SLEW_CTL_2
HS mode (100pf
3 : PORT_SLEW_CTL_3
HS mode (Cb<100pf,1.71
End of enumeration elements list.
PORT_IB_MODE_SEL : This field selects the input buffer reference. The size (1 or 2 bits) and functionality is dependent on the IO cell. For GPIOv2 IO cells, bit PORT_IB_MODE_SEL[1] is not used (GPIOv2 IO cell replaces GPIO IO cell): '0'/'2': CMOS input buffer (PORT_VTRIP_SEL is '0'), LVTTL input buffer (PORT_VTRIP_SEL is '1') '1'/'3': vcchib. For GPIO_OVTv2 and SIOv2 IO cells: '0': CMOS input buffer (PORT_VTRIP_SEL is '0'), LVTTL input buffer (PORT_VTRIP_SEL is '1') '1': vcchib. '2': OVT. '3': Reference (possibly from reference generator cell). For SIO IO cell, this field is present but not used as the SIO IO cell does not provide input buffer mode select functionality (SIOv2 IO cell will replace SIO IO cell, as soon as it is available). For GPIOV1P2 and GPIOV1P2_I2C cells, PC.PORT_IB_MODE_SEL unused. Refer to DS register.
bits : 30 - 61 (32 bit)
access : read-write
Reference generator configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REF_SEL : Reference selection. A reference Voltage vinref is created using a Voltage vddio: '0': vinref = (0 * 13 + 184)/600 * vddio = 184/600 * vddio. '1': vinref = (1 * 13 + 184)/600 * vddio = 197/600 * vddio. '2': vinref = (2 * 13 + 184)/600 * vddio = 210/600 * vddio. ... '31': vinref = (31 * 13 + 184)/600 * vddio = 587/600 * vddio.
bits : 0 - 4 (5 bit)
access : read-write
VREFGEN_EN : Reference generator enable: '0': Disabled. '1': Enabled.
bits : 8 - 16 (9 bit)
access : read-write
Port interrupt configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE0_SEL : Sets which edge will trigger an IRQ for IO pad 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
EDGE1_SEL : Sets which edge will trigger an IRQ for IO pad 1.
bits : 2 - 5 (4 bit)
access : read-write
EDGE2_SEL : Sets which edge will trigger an IRQ for IO pad 2.
bits : 4 - 9 (6 bit)
access : read-write
EDGE3_SEL : Sets which edge will trigger an IRQ for IO pad 3.
bits : 6 - 13 (8 bit)
access : read-write
EDGE4_SEL : Sets which edge will trigger an IRQ for IO pad 4.
bits : 8 - 17 (10 bit)
access : read-write
EDGE5_SEL : Sets which edge will trigger an IRQ for IO pad 5.
bits : 10 - 21 (12 bit)
access : read-write
EDGE6_SEL : Sets which edge will trigger an IRQ for IO pad 6.
bits : 12 - 25 (14 bit)
access : read-write
EDGE7_SEL : Sets which edge will trigger an IRQ for IO pad 7.
bits : 14 - 29 (16 bit)
access : read-write
FLT_EDGE_SEL : Same for the glitch filtered pin (selected by FLT_SELECT).
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : DISABLE
Disabled
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : BOTH
Both rising and falling edges
End of enumeration elements list.
FLT_SEL : Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.
bits : 18 - 38 (21 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.