CONFIG

PRIV_ROM

SL_CTL0

SL_CTL1

SL_CTL2

SL_CTL3

SL_CTL4

SL_CTL5

SL_CTL6

SL_CTL7

SL_CTL8

SL_CTL9

SL_CTL10

SL_CTL11

SL_CTL12

SL_CTL13

SL_CTL14

SL_CTL15

PRIV_RAM

SL_CTL16

SL_CTL17

SL_CTL18

SL_CTL19

SL_CTL20

SL_CTL21

SL_CTL22

SL_CTL23

PRIV_FLASH

WOUNDING

INT_SEL

INT_MODE

NMI_MODE

FLASH_CTL

ROM_CTL

RAM_CTL

DMAC_CTL

SYSREQ

SYSARG

PRIV_RAM1

RAM1_CTL

MTB_CTL

PROTECTION

VECT_IN_RAM : 0': Vector Table is located at 0x0000:0000 in flash '1': Vector Table is located at 0x2000:0000 in SRAM Note that vectors for RESET and FAULT are always fetched from ROM. Value in flash/RAM is ignored for these vectors.
bits : 0 - 0 (1 bit)
access : read-write

BROM_PROT_LIMIT : Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes. '0': Entire Boot ROM is Privileged. '1': First 256 Bytes are User accessable. ... BROM_PROT_LIMIT >= 'Boot ROM partition capacity': Entire Boot ROM partition is user mode accessible.
bits : 0 - 7 (8 bit)
access : read-write

SROM_PROT_LIMIT : Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes. The limit is wrt. the start of the ROM memory (start of the Boot ROM partition). SROM_PROT_LIMIT * 256 Byte <= 'Boot ROM partition capacity': Entire System ROM is Privileged. SROM_PROT_LIMIT * 256 Byte > 'Boot ROM partition capacity': First SROM_PROT_LIMIT * 256 - 'Boot ROM partition capacity' Bytes are User accessable. ... SROM_PROT_LIMIT >= 'ROM capacity': Entire System ROM is user mode accessible.
bits : 16 - 41 (26 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

RAM_PROT_LIMIT : Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes. '0': Entire SRAM is Privileged. '1': First 256 Bytes are User accessable. Any number larger than the size of the SRAM indicates that the entire SRAM is user mode accessible.
bits : 0 - 8 (9 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

FLASH_PROT_LIMIT : Indicates the limit where the privileged area of flash starts in increments of 256 Bytes. '0': Entire flash is Privileged. '1': First 256 Bytes are User accessable. Any number larger than the size of the flash indicates that the entire flash is user mode accessible. Note that SuperVisory rows are always User accessable. If FLASH_PROT_LIMIT defines a non-empty privileged area, the boot ROM will assume that a system call table exists at the beginning of the Flash privileged area and use it for all SystemCalls made using SYSREQ.
bits : 0 - 11 (12 bit)
access : read-write

RAM_WOUND : Indicates the amount of accessible RAM 0 memory capacitty in this part. The value in this field is effectively write-once (it is only possible to set bits, not clear them). The remainder portion of SRAM is not accessible and will return an AHB-Lite bus error. '0': entire memory accessible '1': first 1/2 of the memory accessible '2': first 1/4 of the memory accessible '3': first 1/8 of the memory accessible '4': first 1/16 of the memory accessible '5': first 1/32 of the memory accessible '6': first 1/64 of the memory accessible '7': first 1/128 of the memory accessible
bits : 16 - 34 (19 bit)
access : read-write

FLASH_WOUND : Indicates the amount of accessible flash in this part. The value in this field is effectively write-once (it is only possible to set bits, not clear them). The remainder portion of flash is not accessible and will return an AHB-Lite bus error. '0': entire memory accessible '1': first 1/2 of the memory accessible '2': first 1/4 of the memory accessible '3': first 1/8 of the memory accessible '4': first 1/16 of the memory accessible '5': first 1/32 of the memory accessible '6': first 1/64 of the memory accessible '7': first 1/128 of the memory accessible (used for the DEAD protection mode)
bits : 20 - 42 (23 bit)
access : read-write

RAM1_WOUND : Wounding of RAM 1 (see description of RAM_WOUND).
bits : 24 - 50 (27 bit)
access : read-write

DSI : Specifies interrupt source: '0': Fixed Function. '1': DSI. When changing the source of a specific interrupt, it is advised to temporarily disable the interrupt using the CM0 NVIC's CLRENA and SETENA interrupt enable clear and set registers to prevent a spurious interrupt activation. In addition, the CM0 NVIC's CLRPEND interrupt pending clear register should be used clear a pending interrupt before re-enabling the interrupt.
bits : 0 - 31 (32 bit)
access : read-write

DSI_INT_PULSE : Specifies DSI interrupt format: '0': level sensitive i.e. no pulse generator. '1': pulse generator on rising edge.
bits : 0 - 31 (32 bit)
access : read-write

DSI_NMI_PULSE : Specifies DSI NMI format: '0': level sensitive i.e. no pulse generator. '1': pulse generator on rising edge.
bits : 0 - 0 (1 bit)
access : read-write

FLASH_WS : Amount of ROM wait states: '0': 0 wait states (fast flash: [0, 24] MHz system frequency, slow flash: [0, 16] MHz system frequency) '1': 1 wait state (fast flash: [24, 48] MHz system frequency, slow flash: [16, 32] MHz system frequency) '2': 2 wait states (slow flash: [32, 48] MHz system frequency) '3': 3 wait states (can be used to give more time for flash access if 2 wait states are not sufficient)
bits : 0 - 1 (2 bit)
access : read-write

PREF_EN : Prefetch enable: '0': disabled. This is a desirable seeting when FLASH_WS is '0' or when predictable execution behavior is required. '1': enabled.
bits : 4 - 8 (5 bit)
access : read-write

FLASH_INVALIDATE : 1': Invalidates the content of the flash controller's buffers.
bits : 8 - 16 (9 bit)
access : read-write

ARB : Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ROM_WS : Amount of ROM wait states: '0': 0 wait states. Use this setting for newer, faster ROM design. Use this setting for older, slower ROM design and frequencies in the range [0, 24] MHz. '1': 1 wait state. Use this setting for older, slower ROM design and frequencies in the range <24, 48] MHz. CPUSSv2 supports two types of ROM memory: an older, slower design (operating at up to 24 MHz) and a newer, faster design (operating at up to 48 MHz). The older design requires 1 wait state for frequencies above 24 MHz. The newer design never requires wait states. All chips after Street Fighter will use the newer design. As a result, all chips after Street Fighter can always use 0 wait states.
bits : 0 - 0 (1 bit)
access : read-write

ARB : Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

ARB : Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

SYSCALL_COMMAND : Opcode of the system call being requested.
bits : 0 - 15 (16 bit)
access : read-write

DIS_RESET_VECT_REL : Disable Reset Vector fetch relocation: '0': CPU accesses to locations 0x0000:0000 - 0x0000:0007 are redirected to ROM. '1': CPU accesses to locations 0x0000:0000 - 0x0000:0007 are made to flash. Note that this field defaults to '0' on reset, ensuring actual reset vector fetches are always made to ROM. Note that this field does not affect DAP accesses. Flash DfT routines may set this bit to '1' to enable uninhibited read-back of programmed data in the first flash page.
bits : 27 - 54 (28 bit)
access : read-write

PRIVILEGED : Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a SystemCall NMI interrupt handler). Any other write to this field sets is to '0'. This field is used as the AHB-Lite hprot[1] signal to implement Cypress proprietary user/privileged modes. These modes are used to enable/disable access to specific MMIO registers and memory regions.
bits : 28 - 56 (29 bit)
access : read-write

ROM_ACCESS_EN : Indicates that executing from Boot ROM is enabled. HW sets this field to '1', on reset or when the SystemCall NMI vector is fetched from Boot ROM. HW sets this field to '0', when the CPU is NOT executing from either Boot or System ROM. This bit is used for debug purposes only.
bits : 29 - 58 (30 bit)
access : read-only

HMASTER_0 : Indicates the source of the write access to the SYSREQ register. '0': CPU write access. '1': DAP write access. HW sets this field when the SYSREQ register is written to and SYSCALL_REQ is '0' (the last time it is set is when SW sets SYSCALL_REQ from '0' to '1').
bits : 30 - 60 (31 bit)
access : read-only

SYSCALL_REQ : CPU/DAP writes a '1' to this field to request a SystemCall. The HMASTER_0 field indicates the source of the write access. Setting this field to '1' immediate results in a NMI. The SystemCall NMI interrupt handler sets this field to '0' after servicing the request.
bits : 31 - 62 (32 bit)
access : read-write

SYSCALL_ARG : Argument to System Call specified in SYSREQ. Semantics of argument depends on system call made. Typically a pointer to a parameter block.
bits : 0 - 31 (32 bit)
access : read-write

RAM_PROT_LIMIT : See description of PRIV_RAM.RAM_PROT_LIMIT. Note that the reset value is 0x1ff, indicating that the complete RAM 1 memory capacity is User accessable.
bits : 0 - 8 (9 bit)
access : read-write

ARB : Arbitration policy (for RAM controller 1): '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky
bits : 16 - 33 (18 bit)
access : read-write

CPU_HALT_TSTOP_EN : 1': Enable CPU Halt to stop MTB trace. ('HALTED' output of CM0+ can stop the trace when high/'1') '0': 'HALTED' output of CM0+ can not strop trace.
bits : 0 - 0 (1 bit)
access : read-write

PROTECTION_MODE : Current protection mode this field is available as a global signal everywhere in the system. Writes to this field are ignored when PROTECTION_LOCK is '1': 0b1xxx: BOOT 0b01xx: KILL 0b001x: PROTECTED 0b0001: OPEN 0b0000: VIRGIN (also used for DEAD mode, but then FLASH_LOCK is also set)
bits : 0 - 3 (4 bit)
access : read-write

FLASH_LOCK : Setting this bit will force SPCIF.ADDRESS.AXA to be ignored, which prevents SM Flash from being erased or overwritten. It is used to indicate the DEAD protection mode. Writes to this field are ignored when PROTECTION_LOCK is '1'
bits : 30 - 60 (31 bit)
access : read-write

PROTECTION_LOCK : Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register. Once '1', this field cannot be cleared.
bits : 31 - 62 (32 bit)
access : read-write