CTRL

CC_BUFF

PERIOD

PERIOD_BUFF

TR_CTRL0

TR_CTRL1

TR_CTRL2

INTR

INTR_SET

INTR_MASK

INTR_MASKED

STATUS

CMD

COUNTER

INTR_CAUSE

CC

COUNTER_ENABLED : Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). - the counter's line outputs ('line_out' and 'line_compl_out').
bits : 0 - 7 (8 bit)
access : read-write

AUTO_RELOAD_CC : Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event.
bits : 0 - 0 (1 bit)
access : read-write

AUTO_RELOAD_PERIOD : Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending siwtch event.
bits : 1 - 2 (2 bit)
access : read-write

PWM_SYNC_KILL : Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.
bits : 2 - 4 (3 bit)
access : read-write

PWM_STOP_ON_KILL : Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only.
bits : 3 - 6 (4 bit)
access : read-write

GENERIC : Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
bits : 8 - 23 (16 bit)
access : read-write

UP_DOWN_MODE : Determines counter direction.
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ONE_SHOT : When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.
bits : 18 - 36 (19 bit)
access : read-write

QUADRATURE_MODE : In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out' i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Counter mode.
bits : 24 - 50 (27 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC : Additional buffer for counter CC register.
bits : 0 - 15 (16 bit)
access : read-write

PERIOD : Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.
bits : 0 - 15 (16 bit)
access : read-write

PERIOD : Additional buffer for counter PERIOD register.
bits : 0 - 15 (16 bit)
access : read-write

CAPTURE_SEL : Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. Input trigger 2 is the first external trigger line (tcpwm.tr_in[0]). In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
bits : 0 - 3 (4 bit)
access : read-write

COUNT_SEL : Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
bits : 4 - 11 (8 bit)
access : read-write

RELOAD_SEL : Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with the value in the TCPWM_CNTn_PERIOD register.
bits : 8 - 19 (12 bit)
access : read-write

STOP_SEL : Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.
bits : 12 - 27 (16 bit)
access : read-write

START_SEL : Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).
bits : 16 - 35 (20 bit)
access : read-write

CAPTURE_EDGE : A capture event will copy the counter value into the CC register.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNT_EDGE : A counter event will increase or decrease the counter by '1'.
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RELOAD_EDGE : A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP_EDGE : A stop event, will stop the counter i.e. it will no longer be running. Stopping will NOT disable the counter.
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

START_EDGE : A start event will start the counter i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CC_MATCH_MODE : Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVERFLOW_MODE : Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNDERFLOW_MODE : Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TC : Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write

CC_MATCH : Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.
bits : 1 - 2 (2 bit)
access : read-write

TC : Write with '1' to set corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

CC_MATCH : Write with '1' to set corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

TC : Mask bit for corresponding bit in interrupt request register.
bits : 0 - 0 (1 bit)
access : read-write

CC_MATCH : Mask bit for corresponding bit in interrupt request register.
bits : 1 - 2 (2 bit)
access : read-write

TC : Logical and of corresponding request and mask bits.
bits : 0 - 0 (1 bit)
access : read-only

CC_MATCH : Logical and of corresponding request and mask bits.
bits : 1 - 2 (2 bit)
access : read-only

DOWN : When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.
bits : 0 - 0 (1 bit)
access : read-only

GENERIC : Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.
bits : 8 - 23 (16 bit)
access : read-only

RUNNING : When '0', the counter is NOT running. When '1', the counter is running.
bits : 31 - 62 (32 bit)
access : read-only

COUNTER_CAPTURE : Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'.
bits : 0 - 7 (8 bit)
access : read-write

COUNTER_RELOAD : Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 8 - 23 (16 bit)
access : read-write

COUNTER_STOP : Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 16 - 39 (24 bit)
access : read-write

COUNTER_START : Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.
bits : 24 - 55 (32 bit)
access : read-write

COUNTER : 16-bit counter value. It is advised to not write to this field when the counter is running.
bits : 0 - 15 (16 bit)
access : read-write

COUNTER_INT : Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'.
bits : 0 - 7 (8 bit)
access : read-only

CC : In CAPTURE mode, captures the counter value. In other modes, compared to counter value.
bits : 0 - 15 (16 bit)
access : read-write