\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :
ID and Revision
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : the ID of LCD controller peripheral is 0xF0F0
bits : 0 - 15 (16 bit)
access : read-only
REVISION : the version number is 0x0001
bits : 16 - 47 (32 bit)
access : read-only
LCD Pin Data Registers
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Divider Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBFR_DIV : Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long.
bits : 0 - 15 (16 bit)
access : read-write
DEAD_DIV : Length of the dead time period in cycles. When set to zero, no dead time period exists.
bits : 16 - 47 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Pin Data Registers
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).
bits : 0 - 31 (32 bit)
access : read-write
LCD Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LS_EN : Low speed (LS) generator enable 1: enable 0: disable
bits : 0 - 0 (1 bit)
access : read-write
HS_EN : High speed (HS) generator enable 1: enable 0: disable
bits : 1 - 2 (2 bit)
access : read-write
LCD_MODE : HS/LS Mode selection
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : LS
Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes).
1 : HS
Select High Speed (system clock) Generator (Works in Active and Sleep power modes only).
End of enumeration elements list.
TYPE : LCD driving waveform type configuration.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : TYPE_A
Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.
1 : TYPE_B
Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0).
End of enumeration elements list.
OP_MODE : Driving mode configuration
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : PWM
PWM Mode
1 : CORRELATION
Digital Correlation Mode
End of enumeration elements list.
BIAS : PWM bias selection
bits : 5 - 11 (7 bit)
access : read-write
Enumeration:
0 : HALF
1/2 Bias
1 : THIRD
1/3 Bias
2 : FOURTH
1/4 Bias (not supported by LS generator)
3 : FIFTH
1/5 Bias (not supported by LS generator)
End of enumeration elements list.
COM_NUM : The number of COM connections minus 2. So: 0: 2 COM's 1: 3 COM's ... 13: 15 COM's 14: 16 COM's 15: undefined
bits : 8 - 19 (12 bit)
access : read-write
LS_EN_STAT : LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator: 1. If LS_EN=0 we are done. Exit the procedure. 2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. 3. Set LS_EN=0. 4. Wait until LS_EN_STAT=0.
bits : 31 - 62 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.