CONFIG

WDT_CTRLOW

WDT_CTRHIGH

WDT_MATCH

WDT_CONFIG

WDT_CONTROL

WDT_CLKEN

STATUS

DPLL

TRIM

LPM_EN : Force block into Low Power Mode: 0: Do not force low power mode (LPM) on 1: Force low power mode (LPM) on
bits : 0 - 0 (1 bit)
access : read-write

LPM_AUTO : Automatically control low power mode (only relevant when LPM_EN=0): 0: Do not enter low power mode (LPM) in DeepSleep 1: Enter low power mode (LPM) in DeepSleep. The logic monitors !act_power_en to determine the device has entered DeepSleep.
bits : 1 - 2 (2 bit)
access : read-write

EXT_INPUT_EN : Disables the load resistor and allows external clock input for pad_xin
bits : 2 - 4 (3 bit)
access : read-write

ENBUS : Test Mode Control bits enbus[7] - N/A enbus[6] - 1=enable both primary Beta Multipliers enbus[5] - N/A enbus[4] - N/A enbus[3] - Load Resistor Control enbus[2] - Load Resistor Control enbus[1] - Load Resistor Control enbus[0] - Load Resistor Control
bits : 16 - 39 (24 bit)
access : read-write

DPLL_ENABLE : Enable DPLL operation. The Oscillator is specified to be stable after 500 ms thus the DPLL should be asserted no sooner than that after IP_ENABLE is set.
bits : 30 - 60 (31 bit)
access : read-write

IP_ENABLE : Master enable for IP - disables both WCO and DPLL
bits : 31 - 62 (32 bit)
access : read-write

WDT_CTR0 : Current value of WDT Counter 0
bits : 0 - 15 (16 bit)
access : read-only

WDT_CTR1 : Current value of WDT Counter 1
bits : 16 - 47 (32 bit)
access : read-only

WDT_CTR2 : Current value of WDT Counter 2
bits : 0 - 31 (32 bit)
access : read-only

WDT_MATCH0 : Match value for Watchdog Counter 0
bits : 0 - 15 (16 bit)
access : read-write

WDT_MATCH1 : Match value for Watchdog Counter 1
bits : 16 - 47 (32 bit)
access : read-write

WDT_MODE0 : Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0).
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_CLEAR0 : Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match
bits : 2 - 4 (3 bit)
access : read-write

WDT_CASCADE0_1 : Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters
bits : 3 - 6 (4 bit)
access : read-write

WDT_MODE1 : Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1).
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_CLEAR1 : Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match
bits : 10 - 20 (11 bit)
access : read-write

WDT_CASCADE1_2 : Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1
bits : 11 - 22 (12 bit)
access : read-write

WDT_MODE2 : Watchdog Counter 2 Mode.
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_BITS2 : Bit to observe for WDT_INT2: 0: Assert when bit0 of WDT_CTR2 toggles (one int every tick) .. 31: Assert when bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)
bits : 24 - 52 (29 bit)
access : read-write

LFCLK_SEL : N/A
bits : 30 - 61 (32 bit)
access : read-write

WDT_ENABLE0 : Enable Counter 0 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period.
bits : 0 - 0 (1 bit)
access : read-write

WDT_ENABLED0 : Indicates actual state of counter. May lag WDT_ENABLE0 by up to 3 LFCLK cycles. After changing WDT_ENABLE0, do not enter DEEPSLEEP mode until this field acknowledges the change.
bits : 1 - 2 (2 bit)
access : read-only

WDT_INT0 : WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODEx=3. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt.
bits : 2 - 4 (3 bit)
access : read-write

WDT_RESET0 : Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT.
bits : 3 - 6 (4 bit)
access : read-write

WDT_ENABLE1 : Enable Counter 1 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period.
bits : 8 - 16 (9 bit)
access : read-write

WDT_ENABLED1 : Indicates actual state of counter. May lag WDT_ENABLE1 by up to 3 LFCLK cycles. After changing WDT_ENABLE1, do not enter DEEPSLEEP mode until this field acknowledges the change.
bits : 9 - 18 (10 bit)
access : read-only

WDT_INT1 : WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt.
bits : 10 - 20 (11 bit)
access : read-write

WDT_RESET1 : Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT.
bits : 11 - 22 (12 bit)
access : read-write

WDT_ENABLE2 : Enable Counter 2 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period.
bits : 16 - 32 (17 bit)
access : read-write

WDT_ENABLED2 : Indicates actual state of counter. May lag WDT_ENABLE2 by up to 3 LFCLK cycles. After changing WDT_ENABLE2, do not enter DEEPSLEEP mode until this field acknowledges the change.
bits : 17 - 34 (18 bit)
access : read-only

WDT_INT2 : WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt.
bits : 18 - 36 (19 bit)
access : read-write

WDT_RESET2 : Resets counter 2 back to 0000_0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT.
bits : 19 - 38 (20 bit)
access : read-write

CLK_WCO_EN_FOR_WDT : Enables the WCO clock for use by the WDT logic. Wait at least 4 WCO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_ILO_EN_FOR_WDT=1
bits : 0 - 0 (1 bit)
access : read-write

CLK_ILO_EN_FOR_WDT : Enables the ILO clock for use by the WDT logic. Wait at least 4 ILO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_WCO_EN_FOR_WDT=1.
bits : 1 - 2 (2 bit)
access : read-write

OUT_BLNK_A : Indicates that output has transitioned - This bit is intended for Test Mode Only and is not a reliable indicator.
bits : 0 - 0 (1 bit)
access : read-only

DPLL_MULT : Multiplier to determine IMO frequency in multiples of the WCO frequency Fimo = (DPLL_MULT + 1) * Fwco
bits : 0 - 10 (11 bit)
access : read-write

DPLL_LF_IGAIN : DPLL Loop Filter Integral Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0
bits : 16 - 34 (19 bit)
access : read-write

DPLL_LF_PGAIN : DPLL Loop Filter Proportionial Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0
bits : 19 - 40 (22 bit)
access : read-write

DPLL_LF_LIMIT : Maximum IMO offset allowed (used to prevent DPLL dynamics from selecting an IMO frequency that the logic cannot support)
bits : 22 - 51 (30 bit)
access : read-write

XGM : Amplifier GM setting - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode. 0x0 - 3370 nA 0x1 - 2620 nA 0x2 - 2250 nA 0x3 - 1500 nA 0x4 - 1870 nA 0x5 - 1120 nA 0x6 - 750 nA 0x7 - 0 nA
bits : 0 - 2 (3 bit)
access : read-write

LPM_GM : GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode.
bits : 4 - 9 (6 bit)
access : read-write