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address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :
Flash/NVL geometry information
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH : Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present, this field provides the flash capacity of all flash macros together: '0': 256 Bytes. '1': 2*256 Bytes. ... '16383': 16384*256 Bytes.
bits : 0 - 13 (14 bit)
access : read-only
SFLASH : Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present, this field provides the supervisory flash capacity of all flash macros together: '0': 256 Bytes. '1': 2*256 Bytes. ... '63': 64*256 Bytes.
bits : 14 - 33 (20 bit)
access : read-only
NUM_FLASH : Number of flash macros (chip dependent): '0': 1 flash macro '1': 2 flash macros '2': 3 flash macros '3': 4 flash macros
bits : 20 - 41 (22 bit)
access : read-only
FLASH_ROW : Page size in 64 Byte multiples (chip dependent): '0': 64 byte '1': 128 byte '2': 192 byte '3': 256 byte The page size is used to detemine the number of Bytes in a page for Flash page based operations (e.g. PGM_PAGE). Note: the field name FLASH_ROW is misleading, as this field specifies the number of Bytes in a page, rather than the number of Bytes in a row. In a single plane flash macro architecture, a page consists of a single row. However, in a multi plane flash macro architecture, a page consists of multiple rows from different planes.
bits : 22 - 45 (24 bit)
access : read-only
NVL : NVLatch size in Byte multiples (chip dependent): '0': 0 Bytes '1': 1 Byte ... '127': 127 Bytes
bits : 24 - 54 (31 bit)
access : read-only
DE_CPD_LP : 0': SRAM busy wait loop has not been copied. '1': Busy wait loop has been written into SRAM.
bits : 31 - 62 (32 bit)
access : read-write
NVL write data register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data to be written to NVLatch array
bits : 0 - 7 (8 bit)
access : read-write
SPCIF interrupt request register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : Timer counter value reaches '0'. Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write
SPCIF interrupt set request register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : Write INTR_SET field with '1' to set corresponding INTR field.
bits : 0 - 0 (1 bit)
access : read-write
SPCIF interrupt mask register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMER : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write
SPCIF interrupt masked request register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMER : Logical and of corresponding request and mask fields.
bits : 0 - 0 (1 bit)
access : read-only
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