CM0_CTL

CM0_CLOCK_CTL

RAM0_CTL0

RAM0_PWR_MACRO_CTL0

RAM0_PWR_MACRO_CTL1

RAM0_PWR_MACRO_CTL2

RAM0_PWR_MACRO_CTL3

RAM0_PWR_MACRO_CTL4

RAM0_PWR_MACRO_CTL5

RAM0_PWR_MACRO_CTL6

RAM0_PWR_MACRO_CTL7

RAM0_PWR_MACRO_CTL8

RAM0_PWR_MACRO_CTL9

RAM0_PWR_MACRO_CTL10

RAM0_PWR_MACRO_CTL11

RAM0_PWR_MACRO_CTL12

RAM0_PWR_MACRO_CTL13

RAM0_PWR_MACRO_CTL14

RAM0_PWR_MACRO_CTL15

RAM1_CTL0

RAM1_PWR_CTL

RAM2_CTL0

RAM2_PWR_CTL

RAM_PWR_DELAY_CTL

ROM_CTL

UDB_PWR_CTL

UDB_PWR_DELAY_CTL

CM0_INT_CTL0

DP_STATUS

BUFF_CTL

DDFT_CTL

CM0_INT_CTL1

SYSTICK_CTL

CM0_INT_CTL2

CM0_VECTOR_TABLE_BASE

CM0_INT_CTL3

CM4_VECTOR_TABLE_BASE

CM0_INT_CTL4

CM0_PC0_HANDLER

CM0_INT_CTL5

CM0_INT_CTL6

CM0_INT_CTL7

IDENTITY

PROTECTION

CM0_NMI_CTL

AP_CTL

MBIST_STAT

CM0_STATUS

CM4_PWR_CTL

CM4_PWR_DELAY_CTL

CM4_STATUS

CM4_CLOCK_CTL

CM4_NMI_CTL

TRIM_ROM_CTL

TRIM_RAM_CTL

SLV_STALL : Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.
bits : 0 - 0 (1 bit)
access : read-write

ENABLED : Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value see CPU user manual for more details).
bits : 1 - 2 (2 bit)
access : read-write

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

SLOW_INT_DIV : Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write

PERI_INT_DIV : Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.
bits : 24 - 55 (32 bit)
access : read-write

SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write

FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

PWR_MODE : Set Power mode for 1 SRAM0 Macro
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write

FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write

PWR_MODE : Set Power mode for SRAM1
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write

FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write

PWR_MODE : Set Power mode for SRAM2
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write

SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies.
bits : 0 - 1 (2 bit)
access : read-write

FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write

PWR_MODE : Set Power mode for UDBs
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only

UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 1.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 2.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 3.
bits : 24 - 55 (32 bit)
access : read-write

SWJ_CONNECTED : Specifies if the SWJ debug port is connected i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active.
bits : 0 - 0 (1 bit)
access : read-only

SWJ_DEBUG_EN : Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled.
bits : 1 - 2 (2 bit)
access : read-only

SWJ_JTAG_SEL : Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected.
bits : 2 - 4 (3 bit)
access : read-only

WRITE_BUFF : Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.
bits : 0 - 0 (1 bit)
access : read-write

DDFT_OUT0_SEL : Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
bits : 0 - 4 (5 bit)
access : read-write

DDFT_OUT1_SEL : Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
bits : 8 - 20 (13 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 4.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 5.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 6.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 7.
bits : 24 - 55 (32 bit)
access : read-write

TENMS : Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.
bits : 0 - 23 (24 bit)
access : read-write

CLOCK_SOURCE : Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.
bits : 24 - 49 (26 bit)
access : read-write

SKEW : Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise.
bits : 30 - 60 (31 bit)
access : read-write

NOREF : Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.
bits : 31 - 62 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 8.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 9.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 10.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 11.
bits : 24 - 55 (32 bit)
access : read-write

ADDR24 : Address of CM0+ vector table. Note: the CM0+ vector table is at an address that is a 256 B multiple.
bits : 8 - 39 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 12.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 13.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 14.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 15.
bits : 24 - 55 (32 bit)
access : read-write

ADDR22 : Address of CM4 vector table. Note: the CM4 vector table is at an address that is a 1024 B multiple.
bits : 10 - 41 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 16.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 17.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 18.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 19.
bits : 24 - 55 (32 bit)
access : read-write

ADDR : Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.
bits : 0 - 31 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 20.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 21.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 22.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 23.
bits : 24 - 55 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 24.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 25.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 26.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 27.
bits : 24 - 55 (32 bit)
access : read-write

MUX0_SEL : System interrupt select for CPU interrupt source 28.
bits : 0 - 7 (8 bit)
access : read-write

MUX1_SEL : System interrupt select for CPU interrupt source 29.
bits : 8 - 23 (16 bit)
access : read-write

MUX2_SEL : System interrupt select for CPU interrupt source 30.
bits : 16 - 39 (24 bit)
access : read-write

MUX3_SEL : System interrupt select for CPU interrupt source 31.
bits : 24 - 55 (32 bit)
access : read-write

P : This field specifies the privileged setting ('0': user mode '1': privileged mode) of the transfer that reads the register.
bits : 0 - 0 (1 bit)
access : read-only

NS : This field specifies the security setting ('0': secure mode '1': non-secure mode) of the transfer that reads the register.
bits : 1 - 2 (2 bit)
access : read-only

PC : This field specifies the protection context of the transfer that reads the register.
bits : 4 - 11 (8 bit)
access : read-only

MS : This field specifies the bus master identifier of the transfer that reads the register.
bits : 8 - 19 (12 bit)
access : read-only