Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :
Identity
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the privileged setting ('0': user mode '1': privileged mode) of the transfer that reads the register.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the security setting ('0': secure mode '1': non-secure mode) of the transfer that reads the register.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context of the transfer that reads the register.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier of the transfer that reads the register.
bits : 8 - 19 (12 bit)
access : read-only
CM4 interrupt 0 status
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 0. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ control
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLV_STALL : Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.
bits : 0 - 0 (1 bit)
access : read-write
ENABLED : Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value see CPU user manual for more details).
bits : 1 - 2 (2 bit)
access : read-write
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
CM0+ status
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLEEPING : Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
bits : 0 - 0 (1 bit)
access : read-only
SLEEPDEEP : Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
bits : 1 - 2 (2 bit)
access : read-only
CM0+ clock control
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_INT_DIV : Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
PERI_INT_DIV : Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.
bits : 24 - 55 (32 bit)
access : read-write
CM4 interrupt 1 status
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM4 interrupt 2 status
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM4 interrupt 3 status
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM4 interrupt 4 status
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 0 status
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 0. Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1'). The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 1 status
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 1. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 2 status
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 2. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 3 status
address_offset : 0x110C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 3. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 4 status
address_offset : 0x1110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 4. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 5 status
address_offset : 0x1114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 6 status
address_offset : 0x1118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ interrupt 7 status
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM0+ activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ vector table base
address_offset : 0x1120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR24 : Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register. Note: the CM0+ vector table is at an address that is a 256 B multiple.
bits : 8 - 39 (32 bit)
access : read-write
CM4 interrupt 5 status
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 5. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM0+ NMI control
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM0+ NMI control
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM0+ NMI control
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM0+ NMI control
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM4 interrupt 6 status
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 6. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM4 interrupt 7 status
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : Lowest CM4 activated system interrupt index for CPU interrupt 7. See description of CM0_INT0_STATUS.
bits : 0 - 9 (10 bit)
access : read-only
SYSTEM_INT_VALID : See description of CM0_INT0_STATUS.
bits : 31 - 62 (32 bit)
access : read-only
CM4 power control
address_offset : 0x1200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Switch CM4 off Power off, clock off, isolate, reset and no retain.
1 : RESET
Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.
2 : RETAINED
Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain.
3 : ENABLED
Switch CM4 on. Power on, clock on, no isolate, no reset and no retain.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
CM4 power control
address_offset : 0x1204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
RAM 0 control
address_offset : 0x1300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
bits : 8 - 17 (10 bit)
access : read-write
ECC_EN : Enable ECC checking: '0': Disabled. '1': Enabled.
bits : 16 - 32 (17 bit)
access : read-write
ECC_AUTO_CORRECT : HW ECC autocorrect functionality: '0': Disabled. '1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected.
bits : 17 - 34 (18 bit)
access : read-write
ECC_INJ_EN : Enable error injection for system SRAM 0. When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0.
bits : 18 - 36 (19 bit)
access : read-write
RAM 0 status
address_offset : 0x1304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WB_EMPTY : Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode. '0': Write buffer NOT empty. '1': Write buffer empty. Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1').
bits : 0 - 0 (1 bit)
access : read-only
RAM 0 power control
address_offset : 0x1340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x134C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x135C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x136C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x1378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 0 power control
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : SRAM Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.
1 : RSVD
undefined
2 : RETAINED
Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents. The SRAM contents will be retained in DeepSleep system power mode.
3 : ENABLED
Enable SRAM for regular operation. The SRAM contents will be retained in DeepSleep system power mode.
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only
RAM 1 control
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : See RAM0_CTL.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : See RAM0_CTL.
bits : 8 - 17 (10 bit)
access : read-write
ECC_EN : See RAM0_CTL.
bits : 16 - 32 (17 bit)
access : read-write
ECC_AUTO_CORRECT : See RAM0_CTL.
bits : 17 - 34 (18 bit)
access : read-write
ECC_INJ_EN : See RAM0_CTL.
bits : 18 - 36 (19 bit)
access : read-write
RAM 1 status
address_offset : 0x1384 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WB_EMPTY : See RAM0_STATUS.
bits : 0 - 0 (1 bit)
access : read-only
RAM 1 power control
address_offset : 0x1388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See RAM0_PWR_MACRO_CTL.
1 : RSVD
undefined
2 : RETAINED
See RAM0_PWR_MACRO_CTL.
3 : ENABLED
See RAM0_PWR_MACRO_CTL.
End of enumeration elements list.
VECTKEYSTAT : See RAM0_PWR_MACRO_CTL.
bits : 16 - 47 (32 bit)
access : read-only
RAM 2 control
address_offset : 0x13A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : See RAM0_CTL.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : See RAM0_CTL.
bits : 8 - 17 (10 bit)
access : read-write
ECC_EN : See RAM0_CTL.
bits : 16 - 32 (17 bit)
access : read-write
ECC_AUTO_CORRECT : See RAM0_CTL.
bits : 17 - 34 (18 bit)
access : read-write
ECC_INJ_EN : See RAM0_CTL.
bits : 18 - 36 (19 bit)
access : read-write
RAM 2 status
address_offset : 0x13A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WB_EMPTY : See RAM0_STATUS.
bits : 0 - 0 (1 bit)
access : read-only
RAM 2 power control
address_offset : 0x13A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Power mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See RAM0_PWR_MACRO_CTL.
1 : RSVD
undefined
2 : RETAINED
See RAM0_PWR_MACRO_CTL.
3 : ENABLED
See RAM0_PWR_MACRO_CTL.
End of enumeration elements list.
VECTKEYSTAT : See RAM0_PWR_MACRO_CTL.
bits : 16 - 47 (32 bit)
access : read-only
Power up delay used for all SRAM power domains
address_offset : 0x13C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles (clk_slow) delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
ROM control
address_offset : 0x13C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_WS : Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. ROM_CTL.SLOW_WS = '0' when clk_hf <=100 MHz. ROM_CTL.SLOW_WS = '1' when 100MHz < clk_hf <=clk_hf_max. Note: clk_hf_max depends on the target device. Refer datasheet.
bits : 0 - 1 (2 bit)
access : read-write
FAST_WS : Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles. ROM_CTL.FAST_WS = '0' when clk_hf <= clk_hf_max.
bits : 8 - 17 (10 bit)
access : read-write
ECC control
address_offset : 0x13C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORD_ADDR : Specifies the word address where an error will be injected. - On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected. This field needs to be written with the offset address within the memory, divided by 4. For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010.
bits : 0 - 24 (25 bit)
access : read-write
PARITY : ECC parity to use for ECC error injection at address WORD_ADDR.
bits : 25 - 56 (32 bit)
access : read-write
Product identifier and version (same as CoreSight RomTables)
address_offset : 0x1400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FAMILY_ID : Family ID. Common ID for a product family.
bits : 0 - 11 (12 bit)
access : read-only
MAJOR_REV : Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able tie-off)
bits : 16 - 35 (20 bit)
access : read-only
MINOR_REV : Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able tie-off)
bits : 20 - 43 (24 bit)
access : read-only
Debug port status
address_offset : 0x1410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWJ_CONNECTED : Specifies if the SWJ debug port is connected i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active.
bits : 0 - 0 (1 bit)
access : read-only
SWJ_DEBUG_EN : Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled.
bits : 1 - 2 (2 bit)
access : read-only
SWJ_JTAG_SEL : Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected.
bits : 2 - 4 (3 bit)
access : read-only
Access port control
address_offset : 0x1414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0_ENABLE : Enables the CM0 AP interface: '0': Disabled. '1': Enabled.
bits : 0 - 0 (1 bit)
access : read-write
CM4_ENABLE : Enables the CM4 AP interface: '0': Disabled. '1': Enabled.
bits : 1 - 2 (2 bit)
access : read-write
SYS_ENABLE : Enables the system AP interface: '0': Disabled. '1': Enabled.
bits : 2 - 4 (3 bit)
access : read-write
CM0_DISABLE : Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.
bits : 16 - 32 (17 bit)
access : read-write
CM4_DISABLE : Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.
bits : 17 - 34 (18 bit)
access : read-write
SYS_DISABLE : Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.
bits : 18 - 36 (19 bit)
access : read-write
Buffer control
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRITE_BUFF : Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.
bits : 0 - 0 (1 bit)
access : read-write
SysTick timer control
address_offset : 0x1600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.
bits : 0 - 23 (24 bit)
access : read-write
CLOCK_SOURCE : Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.
bits : 24 - 49 (26 bit)
access : read-write
SKEW : Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise.
bits : 30 - 60 (31 bit)
access : read-write
NOREF : Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.
bits : 31 - 62 (32 bit)
access : read-write
Memory BIST status
address_offset : 0x1704 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SFP_READY : Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.
bits : 0 - 0 (1 bit)
access : read-only
SFP_FAIL : Report status of the BIST run, only valid if SFP_READY=1
bits : 1 - 2 (2 bit)
access : read-only
Calibration support set and read
address_offset : 0x1800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Read without side effect, write 1 to set
bits : 0 - 31 (32 bit)
access : read-write
Calibration support clear and reset
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Read side effect: when read all bits are cleared, write 1 to clear a specific bit Note: no exception for the debug host, it also causes the read side effect
bits : 0 - 31 (32 bit)
access : read-write
CM4 vector table base
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR22 : Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register. Note: the CM4 vector table is at an address that is a 1024 B multiple.
bits : 10 - 41 (32 bit)
access : read-write
CM0+ protection context control
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALID : Valid fields for the protection context handler CM0_PCi_HANDLER registers: Bit 0: Valid field for CM0_PC0_HANDLER. Bit 1: Valid field for CM0_PC1_HANDLER. Bit 2: Valid field for CM0_PC2_HANDLER. Bit 3: Valid field for CM0_PC3_HANDLER.
bits : 0 - 3 (4 bit)
access : read-write
CM0+ protection context 0 handler
address_offset : 0x2040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ protection context 1 handler
address_offset : 0x2044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the protection context 1 handler.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ protection context 2 handler
address_offset : 0x2048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the protection context 2 handler.
bits : 0 - 31 (32 bit)
access : read-write
CM0+ protection context 3 handler
address_offset : 0x204C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of the protection context 3 handler.
bits : 0 - 31 (32 bit)
access : read-write
Protection status
address_offset : 0x20C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field.
bits : 0 - 2 (3 bit)
access : read-write
ROM trim control
address_offset : 0x2100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : N/A
bits : 0 - 31 (32 bit)
access : read-write
RAM trim control
address_offset : 0x2104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : N/A
bits : 0 - 31 (32 bit)
access : read-write
CM4 NMI control
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM4 NMI control
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM4 NMI control
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
CM4 NMI control
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTEM_INT_IDX : System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
bits : 0 - 9 (10 bit)
access : read-write
UDB power control
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR_MODE : Set Power mode for UDBs
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
See CM4_PWR_CTL
1 : RESET
See CM4_PWR_CTL
2 : RETAINED
See CM4_PWR_CTL
3 : ENABLED
See CM4_PWR_CTL
End of enumeration elements list.
VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
bits : 16 - 47 (32 bit)
access : read-only
UDB power control
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UP : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write
CM4 status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLEEPING : Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
bits : 0 - 0 (1 bit)
access : read-only
SLEEPDEEP : Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
bits : 1 - 2 (2 bit)
access : read-only
PWR_DONE : After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req
bits : 4 - 8 (5 bit)
access : read-only
CM4 clock control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAST_INT_DIV : Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
bits : 8 - 23 (16 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x801C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x802C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x803C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x804C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x805C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x806C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x807C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x808C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x809C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x80FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x810C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x811C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x812C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x813C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x814C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x815C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x816C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x817C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x818C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x819C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x81FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x820C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x821C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x822C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x823C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x824C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x825C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x826C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x827C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x828C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x829C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x82FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x830C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x831C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x832C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x833C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x834C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x835C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x836C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x837C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x838C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x839C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x83FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x840C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x841C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x842C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x843C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x844C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x846C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x847C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x848C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x849C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x84FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x850C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x851C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x852C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x853C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x854C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x855C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x856C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x858C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x859C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x85FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x860C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x861C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x862C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x863C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x864C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x865C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x866C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x867C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x868C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x869C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x86FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x870C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x871C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x872C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x873C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x874C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x875C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x876C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x877C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x878C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x879C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x87FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x880C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x881C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x882C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x883C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x884C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x885C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x886C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x887C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x888C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x889C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x88FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x890C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x891C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x892C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x893C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x894C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x895C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x896C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x897C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x898C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x899C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x89FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8AFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8B9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8BFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8C9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8CFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8D9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8DFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8E9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8ED8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8EFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM0+ system interrupt control
address_offset : 0x8FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA02C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA03C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA04C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA06C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA07C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA08C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA09C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA0FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA76C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA95C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA96C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA97C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xA9FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xABFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAC9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xACFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xADFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAE9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAED0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAED8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAEFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAF9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 system interrupt control
address_offset : 0xAFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU_INT_IDX : N/A
bits : 0 - 2 (3 bit)
access : read-write
CPU_INT_VALID : N/A
bits : 31 - 62 (32 bit)
access : read-write
CM4 control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOC_MASK : CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the ARM architecture does NOT support FPU exceptions i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions. Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'. Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt.
bits : 24 - 48 (25 bit)
access : read-write
DZC_MASK : CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt.
bits : 25 - 50 (26 bit)
access : read-write
OFC_MASK : CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt.
bits : 26 - 52 (27 bit)
access : read-write
UFC_MASK : CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt.
bits : 27 - 54 (28 bit)
access : read-write
IXC_MASK : CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'.
bits : 28 - 56 (29 bit)
access : read-write
IDC_MASK : CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition: '0': The CPU's exception condition does NOT activate the CPU's floating point interrupt. '1': the CPU's exception condition activates the CPU's floating point interrupt. Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'.
bits : 31 - 62 (32 bit)
access : read-write
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