\n
address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :
IPC acquire
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
bits : 0 - 0 (1 bit)
access : read-only
NS : Secure/non-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
SUCCESS : Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
bits : 31 - 62 (32 bit)
access : read-only
Interrupt
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
bits : 16 - 47 (32 bit)
access : read-write
IPC data 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
IPC lock status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P : This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
bits : 0 - 0 (1 bit)
access : read-only
NS : This field specifies the secure/non-secure access control: '0': secure. '1': non-secure.
bits : 1 - 2 (2 bit)
access : read-only
PC : This field specifies the protection context that successfully acquired the lock.
bits : 4 - 11 (8 bit)
access : read-only
MS : This field specifies the bus master identifier that successfully acquired the lock.
bits : 8 - 19 (12 bit)
access : read-only
ACQUIRED : Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.
bits : 31 - 62 (32 bit)
access : read-only
IPC release
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_RELEASE : Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
Interrupt set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : SW writes a '1' to this field to set the corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
IPC notification
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTR_NOTIFY : This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
bits : 0 - 15 (16 bit)
access : write-only
Interrupt mask
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Mask bit for corresponding field in the INTR register.
bits : 0 - 15 (16 bit)
access : read-write
NOTIFY : Mask bit for corresponding field in the INTR register.
bits : 16 - 47 (32 bit)
access : read-write
IPC data 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : This field holds a 32-bit data element that is associated with the IPC structure.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt masked
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELEASE : Logical and of corresponding request and mask bits.
bits : 0 - 15 (16 bit)
access : read-only
NOTIFY : Logical and of corresponding INTR and INTR_MASK fields.
bits : 16 - 47 (32 bit)
access : read-only
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