Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection :
Master 0 protection context control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged setting ('0': user mode '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities.
bits : 0 - 0 (1 bit)
access : read-write
NS : Security setting ('0': secure mode '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed.
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).
bits : 17 - 48 (32 bit)
access : read-write
SMPU region address 0 (slave structure)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
Master control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access). The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds: * On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler: IF (the new PC is the same as MS_CTL.PC) PC is not affected PC_SAVED is not affected. ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC]) An AHB-Lite bus error is generated for the exception handler fetch PC is not affected PC_SAVED is not affected. ELSE PC = 'new PC' PC_SAVED = PC (push operation). * On entry of any other exception/interrupt handler: PC = PC_SAVED PC_SAVED is not affected (pop operation). Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers. Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS.
bits : 0 - 3 (4 bit)
access : read-write
PC_SAVED : Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Note: this field is ONLY used by the CM0+.
bits : 16 - 35 (20 bit)
access : read-write
MPU region address
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
bits : 0 - 7 (8 bit)
access : read-write
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
bits : 8 - 39 (32 bit)
access : read-write
Master 4 protection context control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 5 protection context control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 6 protection context control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 7 protection context control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 8 protection context control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
SMPU region address 1 (master structure)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBREGION_DISABLE : This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
bits : 0 - 7 (8 bit)
access : read-only
ADDR24 : This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
bits : 8 - 39 (32 bit)
access : read-only
Master control read mirror
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 9 protection context control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
SMPU region attributes 1 (master structure)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1' i.e. user read accesses are ALWAYS allowed.
bits : 0 - 0 (1 bit)
access : read-only
UW : User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0' i.e. user execute accesses are NEVER allowed.
bits : 2 - 4 (3 bit)
access : read-only
PR : Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1' i.e. privileged read accesses are ALWAYS allowed.
bits : 3 - 6 (4 bit)
access : read-only
PW : Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0' i.e. privileged execute accesses are NEVER allowed.
bits : 5 - 10 (6 bit)
access : read-only
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only.
bits : 24 - 52 (29 bit)
access : read-only
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled.
bits : 31 - 62 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 10 protection context control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 11 protection context control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 12 protection context control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 13 protection context control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 14 protection context control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 15 protection context control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 1 protection context control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
SMPU region attributes 0 (slave structure)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed).
bits : 2 - 4 (3 bit)
access : read-write
PR : Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed).
bits : 5 - 10 (6 bit)
access : read-write
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
PC_MASK_0 : This field specifies protection context identifier based access control for protection context '0'.
bits : 8 - 16 (9 bit)
access : read-only
PC_MASK_15_TO_1 : This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed.
bits : 9 - 32 (24 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
PC_MATCH : This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
bits : 30 - 60 (31 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
MPU region attrributes
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UR : User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed).
bits : 0 - 0 (1 bit)
access : read-write
UW : User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
bits : 1 - 2 (2 bit)
access : read-write
UX : User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed).
bits : 2 - 4 (3 bit)
access : read-write
PR : Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed).
bits : 3 - 6 (4 bit)
access : read-write
PW : Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
bits : 4 - 8 (5 bit)
access : read-write
PX : Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed).
bits : 5 - 10 (6 bit)
access : read-write
NS : Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
bits : 6 - 12 (7 bit)
access : read-write
REGION_SIZE : This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
bits : 24 - 52 (29 bit)
access : read-write
ENABLED : Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
bits : 31 - 62 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 2 protection context control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master 3 protection context control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : See MS0_CTL.P.
bits : 0 - 0 (1 bit)
access : read-write
NS : See MS0_CTL.NS.
bits : 1 - 2 (2 bit)
access : read-write
PRIO : See MS0_CTL.PRIO
bits : 8 - 17 (10 bit)
access : read-write
PC_MASK_0 : See MS0_CTL.PC_MASK_0.
bits : 16 - 32 (17 bit)
access : read-only
PC_MASK_15_TO_1 : See MS0_CTL.PC_MASK_15_TO_1.
bits : 17 - 48 (32 bit)
access : read-write
Master control read mirror
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
Master control read mirror
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Read-only mirror of MS_CTL.PC
bits : 0 - 3 (4 bit)
access : read-only
PC_SAVED : Read-only mirror of MS_CTL.PC_SAVED
bits : 16 - 35 (20 bit)
access : read-only
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