\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Read to get system status.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software Interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software Interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software Interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
RAMERR1B : RAM 1-Bit Error Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write
RAMERR2B : RAM 2-Bit Error Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write
Read to get the hard-wired chip revision.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Hardwired Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Hardwired Chip Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Hardwired Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write
Read to get the chip revision programmed by feature configuration.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Chip Revision Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Chip Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Chip Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write
Configure the source of the system tick for the M33.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTICEXTCLKEN : SysTick External Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Configure to provide general RAM configuration.
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRFAULTEN : Invalid Address Bus Fault Response Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMECCERRFAULTEN : Two bit ECC Error Bus Fault Response Enable
bits : 5 - 5 (1 bit)
access : read-write
Configure to provide general RAM retention configuration.
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMRETNCTRL : DMEM0 blockset retention control
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ALLON
None of the RAM blocks powered down
1 : BLK0
Power down RAM block 0
2 : BLK1
Power down RAM block 1
End of enumeration elements list.
Read to get status of the DMEM0 ECC error address.
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMEM0ECCADDR : DMEM0 RAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only
Configure to set RAM ECC control.
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMECCEN : RAM ECC Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMECCEWEN : RAM ECC Error Writeback Enable
bits : 1 - 1 (1 bit)
access : read-write
Write to enable interrupts.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
RAMERR1B : RAM 1-bit Error Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
RAMERR2B : RAM 2-bit Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Data in this register is passed to the trusted root firmware upon reset.
address_offset : 0x600 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
access : read-write
Data in this register is passed to the trusted root firmware upon reset.
address_offset : 0x604 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
access : read-write
This register returns the status of the SE managed locks.
address_offset : 0x608 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSLOCK : Bus Lock
bits : 0 - 0 (1 bit)
access : read-only
REGLOCK : Register Lock
bits : 1 - 1 (1 bit)
access : read-only
MFRLOCK : Manufacture Lock
bits : 2 - 2 (1 bit)
access : read-only
ROOTMODELOCK : Root Mode Lock
bits : 4 - 4 (1 bit)
access : read-only
ROOTDBGLOCK : Root Debug Lock
bits : 8 - 8 (1 bit)
access : read-only
USERDBGLOCK : User Invasive Debug Lock
bits : 16 - 16 (1 bit)
access : read-only
USERNIDLOCK : User Non-invasive Debug Lock
bits : 17 - 17 (1 bit)
access : read-only
USERSPIDLOCK : User Secure Invasive Debug Lock
bits : 18 - 18 (1 bit)
access : read-only
USERSPNIDLOCK : User Secure Non-invasive Debug Lock
bits : 19 - 19 (1 bit)
access : read-only
USERDBGAPLOCK : User Debug Access Port Lock
bits : 20 - 20 (1 bit)
access : read-only
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