FLASHC

MAIN_MAP : Specifies mapping of FLASH macro main array. 0: Mapping A. 1: Mapping B. This field is only used when MAIN_BANK_MODE is '1' (dual bank mode).
bits : 8 - 16 (9 bit)
access : read-write

WORK_MAP : Specifies mapping of FLASH macro work array. 0: Mapping A. 1: Mapping B. This field is only used when WORK_BANK_MODE is '1' (dual bank mode).
bits : 9 - 18 (10 bit)
access : read-write

MAIN_BANK_MODE : Specifies bank mode of FLASH macro main array. 0: Single bank mode. 1: Dual bank mode.
bits : 12 - 24 (13 bit)
access : read-write

WORK_BANK_MODE : Specifies bank mode of FLASH macro work array. 0: Single bank mode. 1: Dual bank mode.
bits : 13 - 26 (14 bit)
access : read-write

MAIN_ECC_EN : Enable ECC checking for FLASH main interface: 0: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled.
bits : 16 - 32 (17 bit)
access : read-write

MAIN_ECC_INJ_EN : Enable error injection for FLASH main interface. When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.
bits : 17 - 34 (18 bit)
access : read-write

MAIN_ERR_SILENT : Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro main interface internal error. - FLASH macro main interface non-recoverable ECC error. - FLASH macro main interface recoverable ECC error. - FLASH macro main interface memory hole error.
bits : 18 - 36 (19 bit)
access : read-write

WORK_ECC_EN : Enable ECC checking for FLASH work interface: 0: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported. 1: Enabled.
bits : 20 - 40 (21 bit)
access : read-write

WORK_ECC_INJ_EN : Enable error injection for FLASH work interface. When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.
bits : 21 - 42 (22 bit)
access : read-write

WORK_ERR_SILENT : Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access): 0: Bus transfer has a bus error. 1: Bus transfer does NOT have a bus error i.e. the error is 'silent' In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer. This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error. Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered). Note: fault reporting can be used to identify the error that occurred: - FLASH macro work interface internal error. - FLASH macro work interface non-recoverable ECC error. - FLASH macro work interface recoverable ECC error. - FLASH macro work interface memory hole error.
bits : 22 - 44 (23 bit)
access : read-write

FM_CTL

Flash macro control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_MODE : Requires (IF_SEL|WR_EN)=1 Flash macro mode selection
bits : 0 - 3 (4 bit)
access : read-write

FM_SEQ : Requires (IF_SEL|WR_EN)=1 Flash macro sequence selection
bits : 8 - 17 (10 bit)
access : read-write

DAA_MUX_SEL : Direct memory cell access address.
bits : 16 - 38 (23 bit)
access : read-write

IF_SEL : Interface selection. Specifies the interface that is used for flash memory read operations: 0: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. 1: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. Note: IF_SEL and WR_EN cannot be changed at the same time
bits : 24 - 48 (25 bit)
access : read-write

WR_EN : 0: normal mode 1: Fm Write Enable Note: IF_SEL and WR_EN cannot be changed at the same time
bits : 25 - 50 (26 bit)
access : read-write

GEOMETRY

Regular flash geometry
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROW_COUNT : Number of rows (minus 1): 0: 1 row 1: 2 rows 2: 3 rows ... '65535': 65536 rows
bits : 0 - 15 (16 bit)
access : read-only

BANK_COUNT : Number of banks (minus 1): 0: 1 bank 1: 2 banks ... '255': 256 banks
bits : 16 - 39 (24 bit)
access : read-only

WORD_SIZE_LOG2 : Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 3: 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.
bits : 24 - 51 (28 bit)
access : read-only

PAGE_SIZE_LOG2 : Number of Bytes per page (log 2): 0: 1 Byte 1: 2 Bytes 2: 4 Bytes ... 15: 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.
bits : 28 - 59 (32 bit)
access : read-only

GEOMETRY_SUPERVISORY

Supervisory flash geometry
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROW_COUNT : Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT
bits : 0 - 15 (16 bit)
access : read-only

BANK_COUNT : Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.
bits : 16 - 39 (24 bit)
access : read-only

WORD_SIZE_LOG2 : Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.
bits : 24 - 51 (28 bit)
access : read-only

PAGE_SIZE_LOG2 : Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.
bits : 28 - 59 (32 bit)
access : read-only

ANA_CTL0

Analog control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAC : Trimming of the output margin Voltage as a function of Vpos and Vneg.
bits : 0 - 7 (8 bit)
access : read-write

CSLDAC : Trimming of common source line DAC.
bits : 8 - 18 (11 bit)
access : read-write

FLIP_AMUXBUS_AB : Flips amuxbusa and amuxbusb 0: amuxbusa, amuxbusb 1: amuxbusb, amuxbusb
bits : 11 - 22 (12 bit)
access : read-write

NDAC_MIN : NDAC staircase min value
bits : 12 - 27 (16 bit)
access : read-write

PDAC_MIN : PDAC staircase min value
bits : 16 - 35 (20 bit)
access : read-write

SCALE_PRG_SEQ01 : PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 20 - 41 (22 bit)
access : read-write

SCALE_PRG_SEQ12 : PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 22 - 45 (24 bit)
access : read-write

SCALE_PRG_SEQ23 : PROG and PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 24 - 49 (26 bit)
access : read-write

SCALE_SEQ30 : PROG and PRE_PROG and ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 26 - 53 (28 bit)
access : read-write

SCALE_PRG_PEON : PROG and PRE_PROG: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 28 - 57 (30 bit)
access : read-write

SCALE_PRG_PEOFF : PROG and PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 30 - 61 (32 bit)
access : read-write

ANA_CTL1

Analog control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NDAC_MAX : Ndac Max Value.Trimming of negative pump output Voltage.
bits : 0 - 3 (4 bit)
access : read-write

NDAC_STEP : Ndac step increment
bits : 4 - 11 (8 bit)
access : read-write

PDAC_MAX : Pdac Max Value.Trimming of positive pump output Voltage:
bits : 8 - 19 (12 bit)
access : read-write

PDAC_STEP : Pdac step increment
bits : 12 - 27 (16 bit)
access : read-write

NPDAC_STEP_TIME : Ndac/Pdac step duration: (1uS .. 255uS) * 8 When = 0 N/PDAC_MAX control the pumps
bits : 16 - 39 (24 bit)
access : read-write

NPDAC_ZERO_TIME : Ndac/Pdac LO duration: (1uS .. 255uS) * 8 When 0, N/PDAC don't return to 0
bits : 24 - 55 (32 bit)
access : read-write

WAIT_CTL

Wait State control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAIT_FM_MEM_RD : Number of C interface wait cycles (on 'clk_c') for a read from the memory
bits : 0 - 3 (4 bit)
access : read-write

WAIT_FM_HV_RD : Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit
bits : 8 - 19 (12 bit)
access : read-write

WAIT_FM_HV_WR : Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.
bits : 16 - 34 (19 bit)
access : read-write

FM_RWW_MODE : 00: Full CBUS MODE 01: RWW 10: RWW. R_GRANT is stalling r_bus for the whole program/erase duration
bits : 24 - 49 (26 bit)
access : read-write

LV_SPARE_1 : Spare register
bits : 26 - 52 (27 bit)
access : read-write

DRMM : 0: Normal 1: Test mode to enable Margin mode for 2 rows at a time
bits : 27 - 54 (28 bit)
access : read-write

MBA : 0: Normal 1: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program).
bits : 28 - 56 (29 bit)
access : read-write

PL_SOFT_SET_EN : Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API
bits : 29 - 58 (30 bit)
access : read-write

ECC_CTL

ECC control
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WORD_ADDR : Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated).
bits : 0 - 23 (24 bit)
access : read-write

PARITY : ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.
bits : 24 - 55 (32 bit)
access : read-write

FM_SRAM_ECC_CTL0

eCT Flash SRAM ECC control 0
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_INJ_DATA : 32-bit data for ECC error injection test of eCT Flash SRAM ECC logic.
bits : 0 - 31 (32 bit)
access : read-write

FM_SRAM_ECC_CTL1

eCT Flash SRAM ECC control 1
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_INJ_PARITY : 7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic.
bits : 0 - 6 (7 bit)
access : read-write

FM_SRAM_ECC_CTL2

eCT Flash SRAM ECC control 2
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CORRECTED_DATA : 32-bit corrected data output of the ECC syndrome logic.
bits : 0 - 31 (32 bit)
access : read-only

FM_SRAM_ECC_CTL3

eCT Flash SRAM ECC control 3
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_ENABLE : ECC generation/check enable for eCT Flash SRAM memory.
bits : 0 - 0 (1 bit)
access : read-write

ECC_INJ_EN : eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test: 1. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers. 2. Set the ECC_INJ_EN bit to '1'. 3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle. 4. Check the corrected data in FM_SRAM_ECC_CTL2. 5. Confirm that fault was reported to fault structure, and check syndrome (only applicable if corrupted data was written in step 1). 6. If not finished, start over at 1 with different data.
bits : 4 - 8 (5 bit)
access : read-write

ECC_TEST_FAIL : Status of ECC test. 1 : ECC test failed because eCT Flash macro is busy and using the SRAM. 0: ECC was performed.
bits : 8 - 16 (9 bit)
access : read-only

TIMER_CLK_CTL

Timer prescaler (clk_t to timer clock frequency divider)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_CLOCK_FREQ : Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer. Equal to the frequency in MHz of the timer clock 'clk_t'. Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4' Max clk_t frequency = 100MHz. This field is updated at runtime with the 'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table
bits : 0 - 7 (8 bit)
access : read-write

RGRANT_DELAY_PRG_PEON : PROG and PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 8 - 23 (16 bit)
access : read-write

RGRANT_DELAY_PRG_PEOFF : PROG and PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 16 - 39 (24 bit)
access : read-write

RGRANT_DELAY_PRG_SEQ01 : PROG and PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 24 - 55 (32 bit)
access : read-write

TIMER_CTL

Timer control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIOD : Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.
bits : 0 - 14 (15 bit)
access : read-write

SCALE : Timer tick scale: 0: 1 microsecond. 1: 100 microseconds.
bits : 15 - 30 (16 bit)
access : read-write

AUTO_SEQUENCE : 1': Starts1 the HV automatic sequencing Cleared by HW
bits : 24 - 48 (25 bit)
access : read-write

PRE_PROG : 1 during pre-program operation
bits : 25 - 50 (26 bit)
access : read-write

PRE_PROG_CSL : 0: CSL lines driven by CSL_DAC 1: CSL lines driven by VNEG_G
bits : 26 - 52 (27 bit)
access : read-write

PUMP_EN : Pump enable: 0: disabled 1: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired.
bits : 29 - 58 (30 bit)
access : read-write

ACLK_EN : ACLK enable (generates a single cycle pulse for the FM): 0: disabled 1: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.
bits : 30 - 60 (31 bit)
access : read-write

TIMER_EN : Timer enable: 0: disabled 1: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.
bits : 31 - 62 (32 bit)
access : read-write

ACLK_CTL

MPCON clock
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ACLK_GEN : A write to this register generates the clock pulse for HV control registers (mpcon outputs)
bits : 0 - 0 (1 bit)
access : write-only

FLASH_PWR_CTL

Flash power control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE : Controls 'enable' pin of the Flash memory.
bits : 0 - 0 (1 bit)
access : read-write

ENABLE_HV : Controls 'enable_hv' pin of the Flash memory.
bits : 1 - 2 (2 bit)
access : read-write

STATUS

Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER_ENABLED : This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires 0: timer not running 1: Timer is enabled and not expired yet
bits : 0 - 0 (1 bit)
access : read-only

HV_REGS_ISOLATED : Indicates the isolation status at HV trim and redundancy registers inputs 0: Not isolated, writing permitted 1: isolated writing disabled
bits : 1 - 2 (2 bit)
access : read-only

ILLEGAL_HVOP : Indicates a bulk, sector erase, program has been requested when axa=1 0: no error 1: illegal HV operation error
bits : 2 - 4 (3 bit)
access : read-only

TURBO_N : After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. 0: turbo mode 1: normal mode
bits : 3 - 6 (4 bit)
access : read-only

WR_EN_MON : FM_CTL.WR_EN bit after being synchronized in clk_r domain
bits : 4 - 8 (5 bit)
access : read-only

IF_SEL_MON : FM_CTL.IF_SEL bit after being synchronized in clk_r domain
bits : 5 - 10 (6 bit)
access : read-only

TIMER_STATUS : The actual timer state sync-ed in clk_c domain: 0: timer is not running: 1: timer is running
bits : 6 - 12 (7 bit)
access : read-only

R_GRANT_DELAY_STATUS : 0: R_GRANT_DELAY timer is not running 1: R_GRANT_DELAY timer is running
bits : 7 - 14 (8 bit)
access : read-only

FM_BUSY : 0': FM not busy 1: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations.
bits : 8 - 16 (9 bit)
access : read-only

FM_READY : 0: FM not ready 1: FM ready
bits : 9 - 18 (10 bit)
access : read-only

POS_PUMP_VLO : POS pump VLO
bits : 10 - 20 (11 bit)
access : read-only

NEG_PUMP_VHI : NEG pump VHI
bits : 11 - 22 (12 bit)
access : read-only

RWW : FM Type (Read While Write or Not Read While Write): 0: Non RWW FM Type 1: RWW FM Type
bits : 12 - 24 (13 bit)
access : read-only

MAX_DOUT_WIDTH : Internal memory core max data out size (number of data out bits per column): 0: x128 bits 1: x256 bits
bits : 13 - 26 (14 bit)
access : read-only

SECTOR0_SR : 0: Sector 0 does not contain special rows. The special rows are located in separate special sectors. 1: Sector 0 contains special rows
bits : 14 - 28 (15 bit)
access : read-only

RESET_MM : Test_only, internal node: mpcon reset_mm
bits : 15 - 30 (16 bit)
access : read-only

ROW_ODD : Test_only, internal node: mpcon row_odd
bits : 16 - 32 (17 bit)
access : read-only

ROW_EVEN : Test_only, internal node: mpcon row_even
bits : 17 - 34 (18 bit)
access : read-only

HVOP_SUB_SECTOR_N : Test_only, internal node: mpcon bk_subb
bits : 18 - 36 (19 bit)
access : read-only

HVOP_SECTOR : Test_only, internal node: mpcon bk_sec
bits : 19 - 38 (20 bit)
access : read-only

HVOP_BULK_ALL : Test_only, internal node: mpcon bk_all
bits : 20 - 40 (21 bit)
access : read-only

CBUS_RA_MATCH : Test_only, internal node: mpcon ra match
bits : 21 - 42 (22 bit)
access : read-only

CBUS_RED_ROW_EN : Test_only, internal node: mpcon red_row_en
bits : 22 - 44 (23 bit)
access : read-only

RQ_ERROR : Test_only, internal node: rq_error sync-de in clk_c domain
bits : 23 - 46 (24 bit)
access : read-only

PUMP_PDAC : Test_only, internal node: regif pdac outputs to pos pump
bits : 24 - 51 (28 bit)
access : read-only

PUMP_NDAC : Test_only, internal node: regif ndac outputs to pos pump
bits : 28 - 59 (32 bit)
access : read-only

INTR

Interrupt
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_EXPIRED : Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.
bits : 0 - 0 (1 bit)
access : read-write

CM0_CA_CTL0

CM0+ cache control
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM_ECC_EN : Enable ECC checking for cache accesses: 0: Disabled. 1: Enabled.
bits : 0 - 0 (1 bit)
access : read-write

RAM_ECC_INJ_EN : Enable error injection for cache. When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address.
bits : 1 - 2 (2 bit)
access : read-write

WAY : Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.
bits : 16 - 33 (18 bit)
access : read-write

SET_ADDR : Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.
bits : 24 - 50 (27 bit)
access : read-write

PREF_EN : Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled i.e. ENABLED is '1'.
bits : 30 - 60 (31 bit)
access : read-write

CA_EN : Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled.
bits : 31 - 62 (32 bit)
access : read-write

CM0_CA_CTL1

CM0+ cache control
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_MODE : Specifies power mode for CM0 cache. The following sequnece should be followed for turning OFF/ON the cache SRAM. Turn OFF sequence: a) Write CM0_CA_CTL0 to disable cache. b) Write CM0_CA_CTL1 to turn OFF cache SRAM. Turn ON sequence: a) Write CM0_CA_CTL1 to turn ON cache SRAM. b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles. c) Write CM0_CA_CTL0 to enable cache.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : OFF

Power OFF the CM0 cache SRAM.

1 : RSVD

Undefined

2 : RETAINED

Put CM0 cache SRAM in retained mode.

3 : ENABLED

Enable/Turn ON the CM0 cache SRAM.

End of enumeration elements list.

VECTKEYSTAT : Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.
bits : 16 - 47 (32 bit)
access : read-only

CM0_CA_CTL2

CM0+ cache control
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRUP_DELAY : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write

INTR_SET

Interrupt set
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_EXPIRED : Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).
bits : 0 - 0 (1 bit)
access : read-write

CM0_CA_STATUS0

CM0+ cache status 0
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VALID32 : Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
bits : 0 - 31 (32 bit)
access : read-only

CM0_CA_STATUS1

CM0+ cache status 1
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAG : Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
bits : 0 - 31 (32 bit)
access : read-only

CM0_CA_STATUS2

CM0+ cache status 2
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LRU : Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3.
bits : 0 - 5 (6 bit)
access : read-only

CM0_STATUS

CM0+ interface status
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAIN_INTERNAL_ERR : Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.
bits : 0 - 0 (1 bit)
access : read-write

WORK_INTERNAL_ERR : See CM0_STATUS.MAIN_INTERNAL_ERROR.
bits : 1 - 2 (2 bit)
access : read-write

INTR_MASK

Interrupt mask
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER_EXPIRED : Mask for corresponding field in INTR register.
bits : 0 - 0 (1 bit)
access : read-write

CM4_CA_CTL0

CM4 cache control
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM_ECC_EN : See CM0_CA_CTL.
bits : 0 - 0 (1 bit)
access : read-write

RAM_ECC_INJ_EN : See CM0_CA_CTL.
bits : 1 - 2 (2 bit)
access : read-write

WAY : See CM0_CA_CTL.
bits : 16 - 33 (18 bit)
access : read-write

SET_ADDR : See CM0_CA_CTL.
bits : 24 - 50 (27 bit)
access : read-write

PREF_EN : See CM0_CA_CTL.
bits : 30 - 60 (31 bit)
access : read-write

CA_EN : See CM0_CA_CTL.
bits : 31 - 62 (32 bit)
access : read-write

CM4_CA_CTL1

CM4 cache control
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_MODE : Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : OFF

See CM0_CA_CTL1

1 : RSVD

Undefined

2 : RETAINED

See CM0_CA_CTL1

3 : ENABLED

See CM0_CA_CTL1

End of enumeration elements list.

CM4_CA_CTL2

CM4 cache control
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRUP_DELAY : Number clock cycles delay needed after power domain power up
bits : 0 - 9 (10 bit)
access : read-write

INTR_MASKED

Interrupt masked
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER_EXPIRED : Logical and of corresponding request and mask fields.
bits : 0 - 0 (1 bit)
access : read-only

CM4_CA_STATUS0

CM4 cache status 0
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VALID32 : See CM0_CA_STATUS0.
bits : 0 - 31 (32 bit)
access : read-only

CM4_CA_STATUS1

CM4 cache status 1
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAG : See CM0_CA_STATUS1.
bits : 0 - 31 (32 bit)
access : read-only

CM4_CA_STATUS2

CM4 cache status 2
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LRU : See CM0_CA_STATUS2.
bits : 0 - 5 (6 bit)
access : read-only

CM4_STATUS

CM4 interface status
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAIN_INTERNAL_ERR : Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP). SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error. Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.
bits : 0 - 0 (1 bit)
access : read-write

WORK_INTERNAL_ERR : See CM4_STATUS.MAIN_INTERNAL_ERROR.
bits : 1 - 2 (2 bit)
access : read-write

CAL_CTL0

Cal control BG LO trim bits
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCT_TRIM_LO_HV : LO Bandgap Voltage Temperature Compensation trim control.
bits : 0 - 4 (5 bit)
access : read-write

CDAC_LO_HV : LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.
bits : 5 - 12 (8 bit)
access : read-write

VBG_TRIM_LO_HV : LO Bandgap Voltage trim control.
bits : 8 - 20 (13 bit)
access : read-write

VBG_TC_TRIM_LO_HV : LO Bandgap Voltage Temperature Compensation trim control
bits : 13 - 28 (16 bit)
access : read-write

ICREF_TC_TRIM_LO_HV : LO Bandgap Current Temperature Compensation trim control
bits : 16 - 34 (19 bit)
access : read-write

IPREF_TRIMA_LO_HV : Adds 100-150nA boost on IPREF_LO
bits : 19 - 38 (20 bit)
access : read-write

CRYPTO_BUFF_CTL

Cryptography buffer control
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : Prefetch enable: 0: Disabled. 1: Enabled. A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer. For eCT work Flash, prefetch will not be done.
bits : 30 - 60 (31 bit)
access : read-write

CAL_CTL1

Cal control BG HI trim bits
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCT_TRIM_HI_HV : HI Bandgap Voltage Temperature Compensation trim control.
bits : 0 - 4 (5 bit)
access : read-write

CDAC_HI_HV : HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.
bits : 5 - 12 (8 bit)
access : read-write

VBG_TRIM_HI_HV : HI Bandgap Voltage trim control.
bits : 8 - 20 (13 bit)
access : read-write

VBG_TC_TRIM_HI_HV : HI Bandgap Voltage Temperature Compensation trim control.
bits : 13 - 28 (16 bit)
access : read-write

ICREF_TC_TRIM_HI_HV : HI Bandgap Current Temperature Compensation trim control.
bits : 16 - 34 (19 bit)
access : read-write

IPREF_TRIMA_HI_HV : Adds 100-150nA boost on IPREF_HI
bits : 19 - 38 (20 bit)
access : read-write

CAL_CTL2

Cal control BG LO and HI trim bits
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICREF_TRIM_LO_HV : LO Bandgap Current trim control.
bits : 0 - 4 (5 bit)
access : read-write

ICREF_TRIM_HI_HV : HI Bandgap Current trim control.
bits : 5 - 14 (10 bit)
access : read-write

IPREF_TRIM_LO_HV : LO Bandgap IPTAT trim control.
bits : 10 - 24 (15 bit)
access : read-write

IPREF_TRIM_HI_HV : HI Bandgap IPTAT trim control.
bits : 15 - 34 (20 bit)
access : read-write

DW0_BUFF_CTL

Datawire 0 buffer control
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write

CAL_CTL3

Cal control osc trim bits, idac, sdac, itim
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC_TRIM_HV : Flash macro pump clock trim control.
bits : 0 - 3 (4 bit)
access : read-write

OSC_RANGE_TRIM_HV : 0: Oscillator High Frequency Range 1: Oscillator Low Frequency range
bits : 4 - 8 (5 bit)
access : read-write

VPROT_ACT_HV : Forces VPROT in active mode all the time
bits : 5 - 10 (6 bit)
access : read-write

IPREF_TC_HV : 0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA 1: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA
bits : 6 - 12 (7 bit)
access : read-write

VREF_SEL_HV : Voltage reference: 0: internal bandgap reference 1: external voltage reference
bits : 7 - 14 (8 bit)
access : read-write

IREF_SEL_HV : Current reference: 0: internal current reference 1: external current reference
bits : 8 - 16 (9 bit)
access : read-write

REG_ACT_HV : 0: VBST regulator will operate in active/standby mode based on control signal. 1: Forces the VBST regulator in active mode all the time
bits : 9 - 18 (10 bit)
access : read-write

FDIV_TRIM_HV : FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby. Following are the clock frequencies seen by doubler 00: F = 1MHz 01: F = 0.5MHz 10: F = 2MHz 11: F = 4MHz
bits : 10 - 21 (12 bit)
access : read-write

VDDHI_HV : 0: vdd < 2.3V 1: vdd >= 2.3V '0' setting can used for vdd > 2.3V also, but with a current penalty.
bits : 12 - 24 (13 bit)
access : read-write

TURBO_PULSEW_HV : Turbo pulse width trim (Typical) 00: 40 us 01: 20 us 10: 15 us 11: 8 us
bits : 13 - 27 (15 bit)
access : read-write

BGLO_EN_HV : 0: Normal (Automatic change over from HI to LO) 1: Force enable LO Bandgap
bits : 15 - 30 (16 bit)
access : read-write

BGHI_EN_HV : 0: Normal (Automatic change over from HI to LO) 1: Force enable HI Bandgap When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active
bits : 16 - 32 (17 bit)
access : read-write

CL_ISO_DIS_HV : 0: The internal logic controls the CL isolation 1: Forces CL bypass
bits : 17 - 34 (18 bit)
access : read-write

R_GRANT_EN_HV : 0: r_grant handshake disabled, r_grant always 1. 1: r_grand handshake enabled
bits : 18 - 36 (19 bit)
access : read-write

LP_ULP_SW_HV : LP<-->ULP switch for trim signals: 0: LP 1: ULP
bits : 19 - 38 (20 bit)
access : read-write

CAL_CTL4

Cal Control Vlim, SA, fdiv, reg_act
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLIM_TRIM_ULP_HV : VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV
bits : 0 - 1 (2 bit)
access : read-write

IDAC_ULP_HV : Sets the sense current reference offset value. Refer to trim tables for details.
bits : 2 - 7 (6 bit)
access : read-write

SDAC_ULP_HV : Sets the sense current reference temp slope. Refer to trim tables for details.
bits : 6 - 13 (8 bit)
access : read-write

ITIM_ULP_HV : Trimming of timing current
bits : 8 - 20 (13 bit)
access : read-write

FM_READY_DEL_ULP_HV : 00: Default : delay 1ns 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us
bits : 13 - 27 (15 bit)
access : read-write

SPARE451_ULP_HV : N/A
bits : 15 - 30 (16 bit)
access : read-write

READY_RESTART_N_HV : Toggle: 1-->0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only.
bits : 16 - 32 (17 bit)
access : read-write

VBST_S_DIS_HV : 0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL. 1: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector.
bits : 17 - 34 (18 bit)
access : read-write

AUTO_HVPULSE_HV : 0: HV Pulse controlled by FW 1: HV Pulse controlled by Hardware
bits : 18 - 36 (19 bit)
access : read-write

UGB_EN_HV : UGB enable in TM control
bits : 19 - 38 (20 bit)
access : read-write

DW1_BUFF_CTL

Datawire 1 buffer control
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write

CAL_CTL5

Cal control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLIM_TRIM_LP_HV : VLIM_TRIM[1:0]: 00: V2 = 650mV 01: V2 = 600mV 10: V2 = 750mV 11: V2 = 700mV
bits : 0 - 1 (2 bit)
access : read-write

IDAC_LP_HV : Sets the sense current reference offset value. Refer to trim tables for details.
bits : 2 - 7 (6 bit)
access : read-write

SDAC_LP_HV : Sets the sense current reference temp slope. Refer to trim tables for details.
bits : 6 - 13 (8 bit)
access : read-write

ITIM_LP_HV : Trimming of timing current
bits : 8 - 20 (13 bit)
access : read-write

FM_READY_DEL_LP_HV : 00: Delayed by 1us 01: Delayed by 1.5us 10: Delayed by 2.0us 11: Delayed by 2.5us
bits : 13 - 27 (15 bit)
access : read-write

SPARE451_LP_HV : N/A
bits : 15 - 30 (16 bit)
access : read-write

SPARE52_HV : N/A
bits : 16 - 33 (18 bit)
access : read-write

AMUX_SEL_HV : Amux Select in AMUX_UGB 00: Bypass UGB for both amuxbusa and amuxbusb 01: Bypass UGB for amuxbusb while passing amuxbusa through UGB. 10: Bypass UGB for amuxbusa while passing amuxbusb through UGB. 11: UGB Calibrate mode
bits : 18 - 37 (20 bit)
access : read-write

CAL_CTL6

SA trim LP/ULP
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SA_CTL_TRIM_T1_ULP_HV : clk_trk delay
bits : 0 - 0 (1 bit)
access : read-write

SA_CTL_TRIM_T4_ULP_HV : SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_ULP_HV<1:0> = eqc (eq cap trim)
bits : 1 - 4 (4 bit)
access : read-write

SA_CTL_TRIM_T5_ULP_HV : SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_ULP_HV<1:0> = evc (integration cap trim)
bits : 4 - 10 (7 bit)
access : read-write

SA_CTL_TRIM_T6_ULP_HV : SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_ULP_HV<0> = ecn (enable cap trim)
bits : 7 - 15 (9 bit)
access : read-write

SA_CTL_TRIM_T8_ULP_HV : saen3 pulse width trim (Current trim)
bits : 9 - 18 (10 bit)
access : read-write

SA_CTL_TRIM_T1_LP_HV : clk_trk delay
bits : 10 - 20 (11 bit)
access : read-write

SA_CTL_TRIM_T4_LP_HV : SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim) SA_CTL_TRIM_T4_LP_HV<1:0> = eqc (eq cap trim)
bits : 11 - 24 (14 bit)
access : read-write

SA_CTL_TRIM_T5_LP_HV : SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim) SA_CTL_TRIM_T5_LP_HV<1:0> = evc (integration cap trim)
bits : 14 - 30 (17 bit)
access : read-write

SA_CTL_TRIM_T6_LP_HV : SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim) SA_CTL_TRIM_T6_LP_HV<0> = ecn (enable cap trim)
bits : 17 - 35 (19 bit)
access : read-write

SA_CTL_TRIM_T8_LP_HV : saen3 pulse width trim (Current trim)
bits : 19 - 38 (20 bit)
access : read-write

DMAC_BUFF_CTL

DMA controller buffer control
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write

CAL_CTL7

Cal control
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERSX8_CLK_SEL_HV : Clock frequency into the ersx8 shift register block 00: Oscillator clock 01: Oscillator clock / 2 10: Oscillator clock / 4 11: Oscillator clock
bits : 0 - 1 (2 bit)
access : read-write

FM_ACTIVE_HV : 0: Normal operation 1: Forces FM SYS in active mode
bits : 2 - 4 (3 bit)
access : read-write

TURBO_EXT_HV : 0: Normal operation 1: Uses external turbo pulse
bits : 3 - 6 (4 bit)
access : read-write

NPDAC_HWCTL_DIS_HV : 0': ndac, pdac staircase hardware controlled 1: ndac, pdac staircase disabled. Enables FW control.
bits : 4 - 8 (5 bit)
access : read-write

FM_READY_DIS_HV : 0': fm ready is enabled 1: fm ready is disabled (fm_ready is always '1')
bits : 5 - 10 (6 bit)
access : read-write

ERSX8_EN_ALL_HV : 0': Staggered turn on/off of GWL 1: GWL are turned on/off at the same time (old FM legacy)
bits : 6 - 12 (7 bit)
access : read-write

DISABLE_LOAD_ONCE_HV : 0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register. 1: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register.
bits : 7 - 14 (8 bit)
access : read-write

SPARE7_HV : N/A
bits : 8 - 17 (10 bit)
access : read-write

SPARE7_ULP_HV : N/A
bits : 10 - 24 (15 bit)
access : read-write

SPARE7_LP_HV : N/A
bits : 15 - 34 (20 bit)
access : read-write

EXT_MS0_BUFF_CTL

External master 0 buffer control
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write

EXT_MS1_BUFF_CTL

External master 1 buffer control
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PREF_EN : See CRYPTO_BUFF_CTL.
bits : 30 - 60 (31 bit)
access : read-write

FM_PL_WRDATA_ALL

Flash macro write page latches all
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA32 : Write all high Voltage page latches with the same 32-bit data in a single write cycle Read always returns 0.
bits : 0 - 31 (32 bit)
access : read-write

FLASH_CMD

Command
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INV : Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.
bits : 0 - 0 (1 bit)
access : read-write

BUFF_INV : Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches.
bits : 1 - 2 (2 bit)
access : read-write

FM_ADDR

Flash macro address
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RA : Row address.
bits : 0 - 15 (16 bit)
access : read-write

BA : Bank address.
bits : 16 - 39 (24 bit)
access : read-write

AXA : Auxiliary address field: 0: regular flash memory. 1: supervisory flash memory.
bits : 24 - 48 (25 bit)
access : read-write

RED_CTL01

Redundancy Control normal sectors 0,1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_ADDR_0 : Bad Row Pair Address for Sector 0
bits : 0 - 7 (8 bit)
access : read-write

RED_EN_0 : 1: Redundancy Enable for Sector 0
bits : 8 - 16 (9 bit)
access : read-write

RED_ADDR_1 : Bad Row Pair Address for Sector 1
bits : 16 - 39 (24 bit)
access : read-write

RED_EN_1 : 1: Redundancy Enable for Sector 1
bits : 24 - 48 (25 bit)
access : read-write

FM_PL_DATA0

Flash macro Page Latches data
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA32 : Four page latch Bytes When reading the page latches it requires FM_CTL.IF_SEL to be '1' Note: the high Voltage page latches are readable for test mode functionality.
bits : 0 - 31 (32 bit)
access : read-write

FM_PL_DATA1

Flash macro Page Latches data
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA2

Flash macro Page Latches data
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA3

Flash macro Page Latches data
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA4

Flash macro Page Latches data
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA5

Flash macro Page Latches data
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA6

Flash macro Page Latches data
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA7

Flash macro Page Latches data
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA8

Flash macro Page Latches data
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA9

Flash macro Page Latches data
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA10

Flash macro Page Latches data
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA11

Flash macro Page Latches data
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA12

Flash macro Page Latches data
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA13

Flash macro Page Latches data
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA14

Flash macro Page Latches data
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA15

Flash macro Page Latches data
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_CTL23

Redundancy Control normal sectors 2,3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_ADDR_2 : Bad Row Pair Address for Sector 2
bits : 0 - 7 (8 bit)
access : read-write

RED_EN_2 : 1: Redundancy Enable for Sector 2
bits : 8 - 16 (9 bit)
access : read-write

RED_ADDR_3 : Bad Row Pair Address for Sector 3
bits : 16 - 39 (24 bit)
access : read-write

RED_EN_3 : 1: Redundancy Enable for Sector 3
bits : 24 - 48 (25 bit)
access : read-write

FM_PL_DATA16

Flash macro Page Latches data
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA17

Flash macro Page Latches data
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA18

Flash macro Page Latches data
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA19

Flash macro Page Latches data
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA20

Flash macro Page Latches data
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA21

Flash macro Page Latches data
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA22

Flash macro Page Latches data
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA23

Flash macro Page Latches data
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA24

Flash macro Page Latches data
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA25

Flash macro Page Latches data
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA26

Flash macro Page Latches data
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA27

Flash macro Page Latches data
address_offset : 0x86C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA28

Flash macro Page Latches data
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA29

Flash macro Page Latches data
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA30

Flash macro Page Latches data
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA31

Flash macro Page Latches data
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_CTL45

Redundancy Control normal sectors 4,5
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_ADDR_4 : Bad Row Pair Address for Sector 4
bits : 0 - 7 (8 bit)
access : read-write

RED_EN_4 : 1: Redundancy Enable for Sector 4
bits : 8 - 16 (9 bit)
access : read-write

RED_ADDR_5 : Bad Row Pair Address for Sector 5
bits : 16 - 39 (24 bit)
access : read-write

RED_EN_5 : 1: Redundancy Enable for Sector 5
bits : 24 - 48 (25 bit)
access : read-write

FM_PL_DATA32

Flash macro Page Latches data
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA33

Flash macro Page Latches data
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA34

Flash macro Page Latches data
address_offset : 0x888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA35

Flash macro Page Latches data
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA36

Flash macro Page Latches data
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA37

Flash macro Page Latches data
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA38

Flash macro Page Latches data
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA39

Flash macro Page Latches data
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA40

Flash macro Page Latches data
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA41

Flash macro Page Latches data
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA42

Flash macro Page Latches data
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA43

Flash macro Page Latches data
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA44

Flash macro Page Latches data
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA45

Flash macro Page Latches data
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA46

Flash macro Page Latches data
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA47

Flash macro Page Latches data
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_CTL67

Redundancy Control normal sectors 6,7
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_ADDR_6 : Bad Row Pair Address for Sector 6
bits : 0 - 7 (8 bit)
access : read-write

RED_EN_6 : 1: Redundancy Enable for Sector 6
bits : 8 - 16 (9 bit)
access : read-write

RED_ADDR_7 : Bad Row Pair Address for Sector 7
bits : 16 - 39 (24 bit)
access : read-write

RED_EN_7 : 1: Redundancy Enable for Sector 7
bits : 24 - 48 (25 bit)
access : read-write

FM_PL_DATA48

Flash macro Page Latches data
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA49

Flash macro Page Latches data
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA50

Flash macro Page Latches data
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA51

Flash macro Page Latches data
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA52

Flash macro Page Latches data
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA53

Flash macro Page Latches data
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA54

Flash macro Page Latches data
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA55

Flash macro Page Latches data
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA56

Flash macro Page Latches data
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA57

Flash macro Page Latches data
address_offset : 0x8E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA58

Flash macro Page Latches data
address_offset : 0x8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA59

Flash macro Page Latches data
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA60

Flash macro Page Latches data
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA61

Flash macro Page Latches data
address_offset : 0x8F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA62

Flash macro Page Latches data
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA63

Flash macro Page Latches data
address_offset : 0x8FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_CTL_SM01

Redundancy Control special sectors 0,1
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RED_ADDR_SM0 : Bad Row Pair Address for Special Sector 0
bits : 0 - 7 (8 bit)
access : read-write

RED_EN_SM0 : Redundancy Enable for Special Sector 0
bits : 8 - 16 (9 bit)
access : read-write

RED_ADDR_SM1 : Bad Row Pair Address for Special Sector 1
bits : 16 - 39 (24 bit)
access : read-write

RED_EN_SM1 : Redundancy Enable for Special Sector 1
bits : 24 - 48 (25 bit)
access : read-write

FM_PL_DATA64

Flash macro Page Latches data
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA65

Flash macro Page Latches data
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA66

Flash macro Page Latches data
address_offset : 0x908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA67

Flash macro Page Latches data
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA68

Flash macro Page Latches data
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA69

Flash macro Page Latches data
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA70

Flash macro Page Latches data
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA71

Flash macro Page Latches data
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA72

Flash macro Page Latches data
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA73

Flash macro Page Latches data
address_offset : 0x924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA74

Flash macro Page Latches data
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA75

Flash macro Page Latches data
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA76

Flash macro Page Latches data
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA77

Flash macro Page Latches data
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA78

Flash macro Page Latches data
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA79

Flash macro Page Latches data
address_offset : 0x93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA80

Flash macro Page Latches data
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA81

Flash macro Page Latches data
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA82

Flash macro Page Latches data
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA83

Flash macro Page Latches data
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA84

Flash macro Page Latches data
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA85

Flash macro Page Latches data
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA86

Flash macro Page Latches data
address_offset : 0x958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA87

Flash macro Page Latches data
address_offset : 0x95C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA88

Flash macro Page Latches data
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA89

Flash macro Page Latches data
address_offset : 0x964 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA90

Flash macro Page Latches data
address_offset : 0x968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA91

Flash macro Page Latches data
address_offset : 0x96C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA92

Flash macro Page Latches data
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA93

Flash macro Page Latches data
address_offset : 0x974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA94

Flash macro Page Latches data
address_offset : 0x978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA95

Flash macro Page Latches data
address_offset : 0x97C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGRANT_DELAY_PRG

R-grant delay for program
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGRANT_DELAY_PRG_SEQ12 : PROG and PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 0 - 7 (8 bit)
access : read-write

RGRANT_DELAY_PRG_SEQ23 : PROG and PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 8 - 23 (16 bit)
access : read-write

RGRANT_DELAY_SEQ30 : PROG and PRE_PROG and ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 16 - 39 (24 bit)
access : read-write

RGRANT_DELAY_CLK : Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay The value of this field is the integer result of 'clk_t frequency / 8'. Example: for clk_t=100 this field is INT(100/8) =12. This field is updated at runtime with the 'SW_RGRANT_DELAY_CLK ' value from the HV parameters table
bits : 24 - 51 (28 bit)
access : read-write

HV_PARAMS_LOADED : 0: HV Pulse common params not loaded 1: HV Pulse common params loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3
bits : 31 - 62 (32 bit)
access : read-write

FM_PL_DATA96

Flash macro Page Latches data
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA97

Flash macro Page Latches data
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA98

Flash macro Page Latches data
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA99

Flash macro Page Latches data
address_offset : 0x98C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA100

Flash macro Page Latches data
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA101

Flash macro Page Latches data
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA102

Flash macro Page Latches data
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA103

Flash macro Page Latches data
address_offset : 0x99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA104

Flash macro Page Latches data
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA105

Flash macro Page Latches data
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA106

Flash macro Page Latches data
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA107

Flash macro Page Latches data
address_offset : 0x9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA108

Flash macro Page Latches data
address_offset : 0x9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA109

Flash macro Page Latches data
address_offset : 0x9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA110

Flash macro Page Latches data
address_offset : 0x9B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA111

Flash macro Page Latches data
address_offset : 0x9BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA112

Flash macro Page Latches data
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA113

Flash macro Page Latches data
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA114

Flash macro Page Latches data
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA115

Flash macro Page Latches data
address_offset : 0x9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA116

Flash macro Page Latches data
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA117

Flash macro Page Latches data
address_offset : 0x9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA118

Flash macro Page Latches data
address_offset : 0x9D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA119

Flash macro Page Latches data
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA120

Flash macro Page Latches data
address_offset : 0x9E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA121

Flash macro Page Latches data
address_offset : 0x9E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA122

Flash macro Page Latches data
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA123

Flash macro Page Latches data
address_offset : 0x9EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA124

Flash macro Page Latches data
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA125

Flash macro Page Latches data
address_offset : 0x9F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA126

Flash macro Page Latches data
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA127

Flash macro Page Latches data
address_offset : 0x9FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PW_SEQ12

HV Pulse Delay for seq 1 and 2 pre
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PW_SEQ1 : Seq1 delay
bits : 0 - 15 (16 bit)
access : read-write

PW_SEQ2_PRE : Seq2 pre delay
bits : 16 - 47 (32 bit)
access : read-write

FM_PL_DATA128

Flash macro Page Latches data
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA129

Flash macro Page Latches data
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA130

Flash macro Page Latches data
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA131

Flash macro Page Latches data
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA132

Flash macro Page Latches data
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA133

Flash macro Page Latches data
address_offset : 0xA14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA134

Flash macro Page Latches data
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA135

Flash macro Page Latches data
address_offset : 0xA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA136

Flash macro Page Latches data
address_offset : 0xA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA137

Flash macro Page Latches data
address_offset : 0xA24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA138

Flash macro Page Latches data
address_offset : 0xA28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA139

Flash macro Page Latches data
address_offset : 0xA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA140

Flash macro Page Latches data
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA141

Flash macro Page Latches data
address_offset : 0xA34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA142

Flash macro Page Latches data
address_offset : 0xA38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA143

Flash macro Page Latches data
address_offset : 0xA3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PW_SEQ23

HV Pulse Delay for seq2 post and seq3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PW_SEQ2_POST : Seq2 post delay
bits : 0 - 15 (16 bit)
access : read-write

PW_SEQ3 : Seq3 delay
bits : 16 - 47 (32 bit)
access : read-write

FM_PL_DATA144

Flash macro Page Latches data
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA145

Flash macro Page Latches data
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA146

Flash macro Page Latches data
address_offset : 0xA48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA147

Flash macro Page Latches data
address_offset : 0xA4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA148

Flash macro Page Latches data
address_offset : 0xA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA149

Flash macro Page Latches data
address_offset : 0xA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA150

Flash macro Page Latches data
address_offset : 0xA58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA151

Flash macro Page Latches data
address_offset : 0xA5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA152

Flash macro Page Latches data
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA153

Flash macro Page Latches data
address_offset : 0xA64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA154

Flash macro Page Latches data
address_offset : 0xA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA155

Flash macro Page Latches data
address_offset : 0xA6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA156

Flash macro Page Latches data
address_offset : 0xA70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA157

Flash macro Page Latches data
address_offset : 0xA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA158

Flash macro Page Latches data
address_offset : 0xA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA159

Flash macro Page Latches data
address_offset : 0xA7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGRANT_SCALE_ERS

R-grant delay scale for erase
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCALE_ERS_SEQ01 : ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 0 - 1 (2 bit)
access : read-write

SCALE_ERS_SEQ12 : ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 2 - 5 (4 bit)
access : read-write

SCALE_ERS_SEQ23 : ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 4 - 9 (6 bit)
access : read-write

SCALE_ERS_PEON : ERASE: Scale for R_GRANT_DELAY on PE On transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 6 - 13 (8 bit)
access : read-write

SCALE_ERS_PEOFF : ERASE: Scale for R_GRANT_DELAY on PE OFF transition: 00: 0.125uS 01: 1uS 10: 10uS 11: 100uS
bits : 8 - 17 (10 bit)
access : read-write

RGRANT_DELAY_ERS_PEON : ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 16 - 39 (24 bit)
access : read-write

RGRANT_DELAY_ERS_PEOFF : ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 24 - 55 (32 bit)
access : read-write

FM_PL_DATA160

Flash macro Page Latches data
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA161

Flash macro Page Latches data
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA162

Flash macro Page Latches data
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA163

Flash macro Page Latches data
address_offset : 0xA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA164

Flash macro Page Latches data
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA165

Flash macro Page Latches data
address_offset : 0xA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA166

Flash macro Page Latches data
address_offset : 0xA98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA167

Flash macro Page Latches data
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA168

Flash macro Page Latches data
address_offset : 0xAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA169

Flash macro Page Latches data
address_offset : 0xAA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA170

Flash macro Page Latches data
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA171

Flash macro Page Latches data
address_offset : 0xAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA172

Flash macro Page Latches data
address_offset : 0xAB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA173

Flash macro Page Latches data
address_offset : 0xAB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA174

Flash macro Page Latches data
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA175

Flash macro Page Latches data
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGRANT_DELAY_ERS

R-grant delay for erase
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGRANT_DELAY_ERS_SEQ01 : ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 0 - 7 (8 bit)
access : read-write

RGRANT_DELAY_ERS_SEQ12 : ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 8 - 23 (16 bit)
access : read-write

RGRANT_DELAY_ERS_SEQ23 : ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23 When = 0 R_GRANT_DELAY control is disabled when IF_SEL=1 R_GRANT_DELAY control is disabled
bits : 16 - 39 (24 bit)
access : read-write

FM_PL_DATA176

Flash macro Page Latches data
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA177

Flash macro Page Latches data
address_offset : 0xAC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA178

Flash macro Page Latches data
address_offset : 0xAC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA179

Flash macro Page Latches data
address_offset : 0xACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA180

Flash macro Page Latches data
address_offset : 0xAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA181

Flash macro Page Latches data
address_offset : 0xAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA182

Flash macro Page Latches data
address_offset : 0xAD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA183

Flash macro Page Latches data
address_offset : 0xADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA184

Flash macro Page Latches data
address_offset : 0xAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA185

Flash macro Page Latches data
address_offset : 0xAE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA186

Flash macro Page Latches data
address_offset : 0xAE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA187

Flash macro Page Latches data
address_offset : 0xAEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA188

Flash macro Page Latches data
address_offset : 0xAF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA189

Flash macro Page Latches data
address_offset : 0xAF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA190

Flash macro Page Latches data
address_offset : 0xAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA191

Flash macro Page Latches data
address_offset : 0xAFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA192

Flash macro Page Latches data
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA193

Flash macro Page Latches data
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA194

Flash macro Page Latches data
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA195

Flash macro Page Latches data
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA196

Flash macro Page Latches data
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA197

Flash macro Page Latches data
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA198

Flash macro Page Latches data
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA199

Flash macro Page Latches data
address_offset : 0xB1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA200

Flash macro Page Latches data
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA201

Flash macro Page Latches data
address_offset : 0xB24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA202

Flash macro Page Latches data
address_offset : 0xB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA203

Flash macro Page Latches data
address_offset : 0xB2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA204

Flash macro Page Latches data
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA205

Flash macro Page Latches data
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA206

Flash macro Page Latches data
address_offset : 0xB38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA207

Flash macro Page Latches data
address_offset : 0xB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA208

Flash macro Page Latches data
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA209

Flash macro Page Latches data
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA210

Flash macro Page Latches data
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA211

Flash macro Page Latches data
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA212

Flash macro Page Latches data
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA213

Flash macro Page Latches data
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA214

Flash macro Page Latches data
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA215

Flash macro Page Latches data
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA216

Flash macro Page Latches data
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA217

Flash macro Page Latches data
address_offset : 0xB64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA218

Flash macro Page Latches data
address_offset : 0xB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA219

Flash macro Page Latches data
address_offset : 0xB6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA220

Flash macro Page Latches data
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA221

Flash macro Page Latches data
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA222

Flash macro Page Latches data
address_offset : 0xB78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA223

Flash macro Page Latches data
address_offset : 0xB7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA224

Flash macro Page Latches data
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA225

Flash macro Page Latches data
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA226

Flash macro Page Latches data
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA227

Flash macro Page Latches data
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA228

Flash macro Page Latches data
address_offset : 0xB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA229

Flash macro Page Latches data
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA230

Flash macro Page Latches data
address_offset : 0xB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA231

Flash macro Page Latches data
address_offset : 0xB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA232

Flash macro Page Latches data
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA233

Flash macro Page Latches data
address_offset : 0xBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA234

Flash macro Page Latches data
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA235

Flash macro Page Latches data
address_offset : 0xBAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA236

Flash macro Page Latches data
address_offset : 0xBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA237

Flash macro Page Latches data
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA238

Flash macro Page Latches data
address_offset : 0xBB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA239

Flash macro Page Latches data
address_offset : 0xBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA240

Flash macro Page Latches data
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA241

Flash macro Page Latches data
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA242

Flash macro Page Latches data
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA243

Flash macro Page Latches data
address_offset : 0xBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA244

Flash macro Page Latches data
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA245

Flash macro Page Latches data
address_offset : 0xBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA246

Flash macro Page Latches data
address_offset : 0xBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA247

Flash macro Page Latches data
address_offset : 0xBDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA248

Flash macro Page Latches data
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA249

Flash macro Page Latches data
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA250

Flash macro Page Latches data
address_offset : 0xBE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA251

Flash macro Page Latches data
address_offset : 0xBEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA252

Flash macro Page Latches data
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA253

Flash macro Page Latches data
address_offset : 0xBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA254

Flash macro Page Latches data
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FM_PL_DATA255

Flash macro Page Latches data
address_offset : 0xBFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOKMARK

Bookmark register - keeps the current FW HV seq
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOKMARK : Used by FW. Keeps the Current HV cycle sequence
bits : 0 - 31 (32 bit)
access : read-write

FM_MEM_DATA0

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA32 : Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is 0: data as specified by the R interface address - IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
bits : 0 - 31 (32 bit)
access : read-only

FM_MEM_DATA1

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA2

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA3

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA4

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA5

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA6

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA7

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA8

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA9

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA10

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA11

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA12

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA13

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA14

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA15

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA16

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA17

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA18

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA19

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA20

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA21

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA22

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA23

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA24

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA25

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA26

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA27

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA28

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA29

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA30

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA31

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA32

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA33

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA34

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA35

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA36

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA37

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA38

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA39

Flash macro memory sense amplifier and column decoder data
address_offset : 0xC9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA40

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA41

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA42

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA43

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA44

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA45

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA46

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA47

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA48

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA49

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA50

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA51

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA52

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA53

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA54

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA55

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA56

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA57

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA58

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA59

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA60

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA61

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA62

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA63

Flash macro memory sense amplifier and column decoder data
address_offset : 0xCFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA64

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA65

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA66

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA67

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA68

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA69

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA70

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA71

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA72

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA73

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA74

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA75

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA76

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA77

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA78

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA79

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA80

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA81

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA82

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA83

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA84

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA85

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA86

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA87

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA88

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA89

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA90

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA91

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA92

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA93

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA94

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA95

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA96

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA97

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA98

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA99

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA100

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA101

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA102

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA103

Flash macro memory sense amplifier and column decoder data
address_offset : 0xD9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA104

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA105

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA106

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA107

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA108

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA109

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA110

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA111

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA112

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA113

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA114

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA115

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA116

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA117

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA118

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA119

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA120

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA121

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA122

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA123

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA124

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA125

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA126

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA127

Flash macro memory sense amplifier and column decoder data
address_offset : 0xDFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA128

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA129

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA130

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA131

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA132

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA133

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA134

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA135

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA136

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA137

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA138

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA139

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA140

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA141

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA142

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA143

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA144

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA145

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA146

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA147

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA148

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA149

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA150

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA151

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA152

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA153

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA154

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA155

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA156

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA157

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA158

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA159

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA160

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA161

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA162

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA163

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA164

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA165

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA166

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA167

Flash macro memory sense amplifier and column decoder data
address_offset : 0xE9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA168

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA169

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA170

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA171

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA172

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA173

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA174

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA175

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA176

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA177

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA178

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA179

Flash macro memory sense amplifier and column decoder data
address_offset : 0xECC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA180

Flash macro memory sense amplifier and column decoder data
address_offset : 0xED0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA181

Flash macro memory sense amplifier and column decoder data
address_offset : 0xED4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA182

Flash macro memory sense amplifier and column decoder data
address_offset : 0xED8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA183

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA184

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA185

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA186

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA187

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA188

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA189

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA190

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA191

Flash macro memory sense amplifier and column decoder data
address_offset : 0xEFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA192

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA193

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA194

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA195

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA196

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA197

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA198

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA199

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA200

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA201

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA202

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA203

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA204

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA205

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA206

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA207

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA208

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA209

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA210

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA211

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA212

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA213

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA214

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA215

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA216

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA217

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA218

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA219

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA220

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA221

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA222

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA223

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA224

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA225

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA226

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA227

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA228

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA229

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA230

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA231

Flash macro memory sense amplifier and column decoder data
address_offset : 0xF9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA232

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA233

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA234

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA235

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA236

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA237

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA238

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA239

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA240

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA241

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA242

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA243

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA244

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA245

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA246

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA247

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA248

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA249

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA250

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA251

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA252

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA253

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA254

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FM_MEM_DATA255

Flash macro memory sense amplifier and column decoder data
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

FLASHC

Peripheral Memory Blocks

Registers

FLASH_CTL

FM_CTL

GEOMETRY

GEOMETRY_SUPERVISORY

ANA_CTL0

ANA_CTL1

WAIT_CTL

ECC_CTL

FM_SRAM_ECC_CTL0

FM_SRAM_ECC_CTL1

FM_SRAM_ECC_CTL2

FM_SRAM_ECC_CTL3

TIMER_CLK_CTL

TIMER_CTL

ACLK_CTL

FLASH_PWR_CTL

STATUS

INTR

CM0_CA_CTL0

CM0_CA_CTL1

CM0_CA_CTL2

INTR_SET

CM0_CA_STATUS0

CM0_CA_STATUS1

CM0_CA_STATUS2

CM0_STATUS

INTR_MASK

CM4_CA_CTL0

CM4_CA_CTL1

CM4_CA_CTL2

INTR_MASKED

CM4_CA_STATUS0

CM4_CA_STATUS1

CM4_CA_STATUS2

CM4_STATUS

CAL_CTL0

CRYPTO_BUFF_CTL

CAL_CTL1

CAL_CTL2

DW0_BUFF_CTL

CAL_CTL3

CAL_CTL4

DW1_BUFF_CTL

CAL_CTL5

CAL_CTL6

DMAC_BUFF_CTL

CAL_CTL7

EXT_MS0_BUFF_CTL

EXT_MS1_BUFF_CTL

FM_PL_WRDATA_ALL

FLASH_CMD

FM_ADDR

RED_CTL01

FM_PL_DATA0

FM_PL_DATA1

FM_PL_DATA2

FM_PL_DATA3

FM_PL_DATA4

FM_PL_DATA5

FM_PL_DATA6

FM_PL_DATA7

FM_PL_DATA8

FM_PL_DATA9

FM_PL_DATA10

FM_PL_DATA11

FM_PL_DATA12

FM_PL_DATA13

FM_PL_DATA14

FM_PL_DATA15

RED_CTL23

FM_PL_DATA16

FM_PL_DATA17

FM_PL_DATA18

FM_PL_DATA19

FM_PL_DATA20

FM_PL_DATA21