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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x321 byte (0x0)
mem_usage : registers
protection :

Registers

ISER

ISPR

ICPR

IPR0

IPR1

IPR2

IPR3

IPR4

IPR5

IPR6

IPR7

ICER


ISER

Interrupt set-enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER ISER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_LP_IRQn BLE_GEN_IRQn FTDF_WAKEUP_IRQn FTDF_GEN_IRQn RFCAL_IRQn COEX_IRQn CRYPTO_IRQn MRM_IRQn UART_IRQn UART2_IRQn I2C_IRQn I2C2_IRQn SPI_IRQn SPI2_IRQn ADC_IRQn KEYBRD_IRQn IRGEN_IRQn WKUP_GPIO_IRQn SWTIM0_IRQn SWTIM1_IRQn QUADEC_IRQn USB_IRQn PCM_IRQn SRC_IN_IRQn SRC_OUT_IRQn VBUS_IRQn DMA_IRQn RF_DIAG_IRQn TRNG_IRQn DCDC_IRQn XTAL16RDY_IRQn Rsvd__irq__n

BLE_WAKEUP_LP_IRQn : BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)
bits : 0 - 0 (1 bit)
access : read-write

BLE_GEN_IRQn : BLE_GEN_IRQn (Interrupt set-enable bit)
bits : 1 - 2 (2 bit)
access : read-write

FTDF_WAKEUP_IRQn : FTDF_WAKEUP_IRQn (Interrupt set-enable bit)
bits : 2 - 4 (3 bit)
access : read-write

FTDF_GEN_IRQn : FTDF_GEN_IRQn (Interrupt set-enable bit)
bits : 3 - 6 (4 bit)
access : read-write

RFCAL_IRQn : RFCAL_IRQn (Interrupt set-enable bit)
bits : 4 - 8 (5 bit)
access : read-write

COEX_IRQn : COEX_IRQn (Interrupt set-enable bit)
bits : 5 - 10 (6 bit)
access : read-write

CRYPTO_IRQn : CRYPTO_IRQn (Interrupt set-enable bit)
bits : 6 - 12 (7 bit)
access : read-write

MRM_IRQn : MRM_IRQn (Interrupt set-enable bit)
bits : 7 - 14 (8 bit)
access : read-write

UART_IRQn : UART_IRQn (Interrupt set-enable bit)
bits : 8 - 16 (9 bit)
access : read-write

UART2_IRQn : UART2_IRQn (Interrupt set-enable bit)
bits : 9 - 18 (10 bit)
access : read-write

I2C_IRQn : I2C_IRQn (Interrupt set-enable bit)
bits : 10 - 20 (11 bit)
access : read-write

I2C2_IRQn : I2C2_IRQn (Interrupt set-enable bit)
bits : 11 - 22 (12 bit)
access : read-write

SPI_IRQn : SPI_IRQn (Interrupt set-enable bit)
bits : 12 - 24 (13 bit)
access : read-write

SPI2_IRQn : SPI2_IRQn (Interrupt set-enable bit)
bits : 13 - 26 (14 bit)
access : read-write

ADC_IRQn : ADC_IRQn (Interrupt set-enable bit)
bits : 14 - 28 (15 bit)
access : read-write

KEYBRD_IRQn : KEYBRD_IRQn (Interrupt set-enable bit)
bits : 15 - 30 (16 bit)
access : read-write

IRGEN_IRQn : IRGEN_IRQn (Interrupt set-enable bit)
bits : 16 - 32 (17 bit)
access : read-write

WKUP_GPIO_IRQn : WKUP_GPIO_IRQn (Interrupt set-enable bit)
bits : 17 - 34 (18 bit)
access : read-write

SWTIM0_IRQn : SWTIM0_IRQn (Interrupt set-enable bit)
bits : 18 - 36 (19 bit)
access : read-write

SWTIM1_IRQn : SWTIM1_IRQn (Interrupt set-enable bit)
bits : 19 - 38 (20 bit)
access : read-write

QUADEC_IRQn : QUADEC_IRQn (Interrupt set-enable bit)
bits : 20 - 40 (21 bit)
access : read-write

USB_IRQn : USB_IRQn (Interrupt set-enable bit)
bits : 21 - 42 (22 bit)
access : read-write

PCM_IRQn : PCM_IRQn (Interrupt set-enable bit)
bits : 22 - 44 (23 bit)
access : read-write

SRC_IN_IRQn : SRC_IN_IRQn (Interrupt set-enable bit)
bits : 23 - 46 (24 bit)
access : read-write

SRC_OUT_IRQn : SRC_OUT_IRQn (Interrupt set-enable bit)
bits : 24 - 48 (25 bit)
access : read-write

VBUS_IRQn : VBUS_IRQn (Interrupt set-enable bit)
bits : 25 - 50 (26 bit)
access : read-write

DMA_IRQn : DMA_IRQn (Interrupt set-enable bit)
bits : 26 - 52 (27 bit)
access : read-write

RF_DIAG_IRQn : RF_DIAG_IRQn (Interrupt set-enable bit)
bits : 27 - 54 (28 bit)
access : read-write

TRNG_IRQn : TRNG_IRQn (Interrupt set-enable bit)
bits : 28 - 56 (29 bit)
access : read-write

DCDC_IRQn : DCDC_IRQn (Interrupt set-enable bit)
bits : 29 - 58 (30 bit)
access : read-write

XTAL16RDY_IRQn : XTAL16RDY_IRQn (Interrupt set-enable bit)
bits : 30 - 60 (31 bit)
access : read-write

Rsvd__irq__n : Rsvd__irq__n (Reserved)
bits : 31 - 62 (32 bit)
access : read-write


ISPR

Interrupt set-pending register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR ISPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_LP_IRQn BLE_GEN_IRQn FTDF_WAKEUP_IRQn FTDF_GEN_IRQn RFCAL_IRQn COEX_IRQn CRYPTO_IRQn MRM_IRQn UART_IRQn UART2_IRQn I2C_IRQn I2C2_IRQn SPI_IRQn SPI2_IRQn ADC_IRQn KEYBRD_IRQn IRGEN_IRQn WKUP_GPIO_IRQn SWTIM0_IRQn SWTIM1_IRQn QUADEC_IRQn USB_IRQn PCM_IRQn SRC_IN_IRQn SRC_OUT_IRQn VBUS_IRQn DMA_IRQn RF_DIAG_IRQn TRNG_IRQn DCDC_IRQn XTAL16RDY_IRQn Rsvd__irq__n

BLE_WAKEUP_LP_IRQn : BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)
bits : 0 - 0 (1 bit)
access : read-write

BLE_GEN_IRQn : BLE_GEN_IRQn (Interrupt set-pending bit)
bits : 1 - 2 (2 bit)
access : read-write

FTDF_WAKEUP_IRQn : FTDF_WAKEUP_IRQn (Interrupt set-pending bit)
bits : 2 - 4 (3 bit)
access : read-write

FTDF_GEN_IRQn : FTDF_GEN_IRQn (Interrupt set-pending bit)
bits : 3 - 6 (4 bit)
access : read-write

RFCAL_IRQn : RFCAL_IRQn (Interrupt set-pending bit)
bits : 4 - 8 (5 bit)
access : read-write

COEX_IRQn : COEX_IRQn (Interrupt set-pending bit)
bits : 5 - 10 (6 bit)
access : read-write

CRYPTO_IRQn : CRYPTO_IRQn (Interrupt set-pending bit)
bits : 6 - 12 (7 bit)
access : read-write

MRM_IRQn : MRM_IRQn (Interrupt set-pending bit)
bits : 7 - 14 (8 bit)
access : read-write

UART_IRQn : UART_IRQn (Interrupt set-pending bit)
bits : 8 - 16 (9 bit)
access : read-write

UART2_IRQn : UART2_IRQn (Interrupt set-pending bit)
bits : 9 - 18 (10 bit)
access : read-write

I2C_IRQn : I2C_IRQn (Interrupt set-pending bit)
bits : 10 - 20 (11 bit)
access : read-write

I2C2_IRQn : I2C2_IRQn (Interrupt set-pending bit)
bits : 11 - 22 (12 bit)
access : read-write

SPI_IRQn : SPI_IRQn (Interrupt set-pending bit)
bits : 12 - 24 (13 bit)
access : read-write

SPI2_IRQn : SPI2_IRQn (Interrupt set-pending bit)
bits : 13 - 26 (14 bit)
access : read-write

ADC_IRQn : ADC_IRQn (Interrupt set-pending bit)
bits : 14 - 28 (15 bit)
access : read-write

KEYBRD_IRQn : KEYBRD_IRQn (Interrupt set-pending bit)
bits : 15 - 30 (16 bit)
access : read-write

IRGEN_IRQn : IRGEN_IRQn (Interrupt set-pending bit)
bits : 16 - 32 (17 bit)
access : read-write

WKUP_GPIO_IRQn : WKUP_GPIO_IRQn (Interrupt set-pending bit)
bits : 17 - 34 (18 bit)
access : read-write

SWTIM0_IRQn : SWTIM0_IRQn (Interrupt set-pending bit)
bits : 18 - 36 (19 bit)
access : read-write

SWTIM1_IRQn : SWTIM1_IRQn (Interrupt set-pending bit)
bits : 19 - 38 (20 bit)
access : read-write

QUADEC_IRQn : QUADEC_IRQn (Interrupt set-pending bit)
bits : 20 - 40 (21 bit)
access : read-write

USB_IRQn : USB_IRQn (Interrupt set-pending bit)
bits : 21 - 42 (22 bit)
access : read-write

PCM_IRQn : PCM_IRQn (Interrupt set-pending bit)
bits : 22 - 44 (23 bit)
access : read-write

SRC_IN_IRQn : SRC_IN_IRQn (Interrupt set-pending bit)
bits : 23 - 46 (24 bit)
access : read-write

SRC_OUT_IRQn : SRC_OUT_IRQn (Interrupt set-pending bit)
bits : 24 - 48 (25 bit)
access : read-write

VBUS_IRQn : VBUS_IRQn (Interrupt set-pending bit)
bits : 25 - 50 (26 bit)
access : read-write

DMA_IRQn : DMA_IRQn (Interrupt set-pending bit)
bits : 26 - 52 (27 bit)
access : read-write

RF_DIAG_IRQn : RF_DIAG_IRQn (Interrupt set-pending bit)
bits : 27 - 54 (28 bit)
access : read-write

TRNG_IRQn : TRNG_IRQn (Interrupt set-pending bit)
bits : 28 - 56 (29 bit)
access : read-write

DCDC_IRQn : DCDC_IRQn (Interrupt set-pending bit)
bits : 29 - 58 (30 bit)
access : read-write

XTAL16RDY_IRQn : XTAL16RDY_IRQn (Interrupt set-pending bit)
bits : 30 - 60 (31 bit)
access : read-write

Rsvd__irq__n : Rsvd__irq__n (Reserved)
bits : 31 - 62 (32 bit)
access : read-write


ICPR

Interrupt clear-pending register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR ICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_LP_IRQn BLE_GEN_IRQn FTDF_WAKEUP_IRQn FTDF_GEN_IRQn RFCAL_IRQn COEX_IRQn CRYPTO_IRQn MRM_IRQn UART_IRQn UART2_IRQn I2C_IRQn I2C2_IRQn SPI_IRQn SPI2_IRQn ADC_IRQn KEYBRD_IRQn IRGEN_IRQn WKUP_GPIO_IRQn SWTIM0_IRQn SWTIM1_IRQn QUADEC_IRQn USB_IRQn PCM_IRQn SRC_IN_IRQn SRC_OUT_IRQn VBUS_IRQn DMA_IRQn RF_DIAG_IRQn TRNG_IRQn DCDC_IRQn XTAL16RDY_IRQn Rsvd__irq__n

BLE_WAKEUP_LP_IRQn : BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)
bits : 0 - 0 (1 bit)
access : read-write

BLE_GEN_IRQn : BLE_GEN_IRQn (Interrupt clear-pending bit)
bits : 1 - 2 (2 bit)
access : read-write

FTDF_WAKEUP_IRQn : FTDF_WAKEUP_IRQn (Interrupt clear-pending bit)
bits : 2 - 4 (3 bit)
access : read-write

FTDF_GEN_IRQn : FTDF_GEN_IRQn (Interrupt clear-pending bit)
bits : 3 - 6 (4 bit)
access : read-write

RFCAL_IRQn : RFCAL_IRQn (Interrupt clear-pending bit)
bits : 4 - 8 (5 bit)
access : read-write

COEX_IRQn : COEX_IRQn (Interrupt clear-pending bit)
bits : 5 - 10 (6 bit)
access : read-write

CRYPTO_IRQn : CRYPTO_IRQn (Interrupt clear-pending bit)
bits : 6 - 12 (7 bit)
access : read-write

MRM_IRQn : MRM_IRQn (Interrupt clear-pending bit)
bits : 7 - 14 (8 bit)
access : read-write

UART_IRQn : UART_IRQn (Interrupt clear-pending bit)
bits : 8 - 16 (9 bit)
access : read-write

UART2_IRQn : UART2_IRQn (Interrupt clear-pending bit)
bits : 9 - 18 (10 bit)
access : read-write

I2C_IRQn : I2C_IRQn (Interrupt clear-pending bit)
bits : 10 - 20 (11 bit)
access : read-write

I2C2_IRQn : I2C2_IRQn (Interrupt clear-pending bit)
bits : 11 - 22 (12 bit)
access : read-write

SPI_IRQn : SPI_IRQn (Interrupt clear-pending bit)
bits : 12 - 24 (13 bit)
access : read-write

SPI2_IRQn : SPI2_IRQn (Interrupt clear-pending bit)
bits : 13 - 26 (14 bit)
access : read-write

ADC_IRQn : ADC_IRQn (Interrupt clear-pending bit)
bits : 14 - 28 (15 bit)
access : read-write

KEYBRD_IRQn : KEYBRD_IRQn (Interrupt clear-pending bit)
bits : 15 - 30 (16 bit)
access : read-write

IRGEN_IRQn : IRGEN_IRQn (Interrupt clear-pending bit)
bits : 16 - 32 (17 bit)
access : read-write

WKUP_GPIO_IRQn : WKUP_GPIO_IRQn (Interrupt clear-pending bit)
bits : 17 - 34 (18 bit)
access : read-write

SWTIM0_IRQn : SWTIM0_IRQn (Interrupt clear-pending bit)
bits : 18 - 36 (19 bit)
access : read-write

SWTIM1_IRQn : SWTIM1_IRQn (Interrupt clear-pending bit)
bits : 19 - 38 (20 bit)
access : read-write

QUADEC_IRQn : QUADEC_IRQn (Interrupt clear-pending bit)
bits : 20 - 40 (21 bit)
access : read-write

USB_IRQn : USB_IRQn (Interrupt clear-pending bit)
bits : 21 - 42 (22 bit)
access : read-write

PCM_IRQn : PCM_IRQn (Interrupt clear-pending bit)
bits : 22 - 44 (23 bit)
access : read-write

SRC_IN_IRQn : SRC_IN_IRQn (Interrupt clear-pending bit)
bits : 23 - 46 (24 bit)
access : read-write

SRC_OUT_IRQn : SRC_OUT_IRQn (Interrupt clear-pending bit)
bits : 24 - 48 (25 bit)
access : read-write

VBUS_IRQn : VBUS_IRQn (Interrupt clear-pending bit)
bits : 25 - 50 (26 bit)
access : read-write

DMA_IRQn : DMA_IRQn (Interrupt clear-pending bit)
bits : 26 - 52 (27 bit)
access : read-write

RF_DIAG_IRQn : RF_DIAG_IRQn (Interrupt clear-pending bit)
bits : 27 - 54 (28 bit)
access : read-write

TRNG_IRQn : TRNG_IRQn (Interrupt clear-pending bit)
bits : 28 - 56 (29 bit)
access : read-write

DCDC_IRQn : DCDC_IRQn (Interrupt clear-pending bit)
bits : 29 - 58 (30 bit)
access : read-write

XTAL16RDY_IRQn : XTAL16RDY_IRQn (Interrupt clear-pending bit)
bits : 30 - 60 (31 bit)
access : read-write

Rsvd__irq__n : Rsvd__irq__n (Reserved)
bits : 31 - 62 (32 bit)
access : read-write


IPR0

Interrupt priority register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_LP_IRQn_prio BLE_GEN_IRQn_prio FTDF_WAKEUP_IRQn_prio FTDF_GEN_IRQn_prio

BLE_WAKEUP_LP_IRQn_prio : BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

BLE_GEN_IRQn_prio : BLE_GEN_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

FTDF_WAKEUP_IRQn_prio : FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

FTDF_GEN_IRQn_prio : FTDF_GEN_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR1

Interrupt priority register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCAL_IRQn_prio COEX_IRQn_prio CRYPTO_IRQn_prio MRM_IRQn_prio

RFCAL_IRQn_prio : RFCAL_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

COEX_IRQn_prio : COEX_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

CRYPTO_IRQn_prio : CRYPTO_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

MRM_IRQn_prio : MRM_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR2

Interrupt priority register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_IRQn_prio UART2_IRQn_prio I2C_IRQn_prio I2C2_IRQn_prio

UART_IRQn_prio : UART_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

UART2_IRQn_prio : UART2_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

I2C_IRQn_prio : I2C_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

I2C2_IRQn_prio : I2C2_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR3

Interrupt priority register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_IRQn_prio SPI2_IRQn_prio ADC_IRQn_prio KEYBRD_IRQn_prio

SPI_IRQn_prio : SPI_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

SPI2_IRQn_prio : SPI2_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

ADC_IRQn_prio : ADC_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

KEYBRD_IRQn_prio : KEYBRD_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR4

Interrupt priority register 4
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR4 IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRGEN_IRQn_prio WKUP_GPIO_IRQn_prio SWTIM0_IRQn_prio SWTIM1_IRQn_prio

IRGEN_IRQn_prio : IRGEN_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

WKUP_GPIO_IRQn_prio : WKUP_GPIO_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

SWTIM0_IRQn_prio : SWTIM0_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

SWTIM1_IRQn_prio : SWTIM1_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR5

Interrupt priority register 5
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR5 IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUADEC_IRQn_prio USB_IRQn_prio PCM_IRQn_prio SRC_IN_IRQn_prio

QUADEC_IRQn_prio : QUADEC_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

USB_IRQn_prio : USB_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

PCM_IRQn_prio : PCM_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

SRC_IN_IRQn_prio : SRC_IN_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR6

Interrupt priority register 6
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR6 IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_OUT_IRQn_prio VBUS_IRQn_prio DMA_IRQn_prio RF_DIAG_IRQn_prio

SRC_OUT_IRQn_prio : SRC_OUT_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

VBUS_IRQn_prio : VBUS_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

DMA_IRQn_prio : DMA_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

RF_DIAG_IRQn_prio : RF_DIAG_IRQn[7:0] bits (Interrupt priority)
bits : 24 - 55 (32 bit)
access : read-write


IPR7

Interrupt priority register 7
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR7 IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRNG_IRQn_prio DCDC_IRQn_prio XTAL16RDY_IRQn_prio RESERVED31_IRQn_DONT_USE

TRNG_IRQn_prio : TRNG_IRQn[7:0] bits (Interrupt priority)
bits : 0 - 7 (8 bit)
access : read-write

DCDC_IRQn_prio : DCDC_IRQn[7:0] bits (Interrupt priority)
bits : 8 - 23 (16 bit)
access : read-write

XTAL16RDY_IRQn_prio : XTAL16RDY_IRQn[7:0] bits (Interrupt priority)
bits : 16 - 39 (24 bit)
access : read-write

RESERVED31_IRQn_DONT_USE : RESERVED31_IRQn[7:0] bits (Reserved)
bits : 24 - 55 (32 bit)
access : read-write


ICER

Interrupt clear-enable register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER ICER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_LP_IRQn BLE_GEN_IRQn FTDF_WAKEUP_IRQn FTDF_GEN_IRQn RFCAL_IRQn COEX_IRQn CRYPTO_IRQn MRM_IRQn UART_IRQn UART2_IRQn I2C_IRQn I2C2_IRQn SPI_IRQn SPI2_IRQn ADC_IRQn KEYBRD_IRQn IRGEN_IRQn WKUP_GPIO_IRQn SWTIM0_IRQn SWTIM1_IRQn QUADEC_IRQn USB_IRQn PCM_IRQn SRC_IN_IRQn SRC_OUT_IRQn VBUS_IRQn DMA_IRQn RF_DIAG_IRQn TRNG_IRQn DCDC_IRQn XTAL16RDY_IRQn Rsvd__irq__n

BLE_WAKEUP_LP_IRQn : BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)
bits : 0 - 0 (1 bit)
access : read-write

BLE_GEN_IRQn : BLE_GEN_IRQn (Interrupt clear-enable bit)
bits : 1 - 2 (2 bit)
access : read-write

FTDF_WAKEUP_IRQn : FTDF_WAKEUP_IRQn (Interrupt clear-enable bit)
bits : 2 - 4 (3 bit)
access : read-write

FTDF_GEN_IRQn : FTDF_GEN_IRQn (Interrupt clear-enable bit)
bits : 3 - 6 (4 bit)
access : read-write

RFCAL_IRQn : RFCAL_IRQn (Interrupt clear-enable bit)
bits : 4 - 8 (5 bit)
access : read-write

COEX_IRQn : COEX_IRQn (Interrupt clear-enable bit)
bits : 5 - 10 (6 bit)
access : read-write

CRYPTO_IRQn : CRYPTO_IRQn (Interrupt clear-enable bit)
bits : 6 - 12 (7 bit)
access : read-write

MRM_IRQn : MRM_IRQn (Interrupt clear-enable bit)
bits : 7 - 14 (8 bit)
access : read-write

UART_IRQn : UART_IRQn (Interrupt clear-enable bit)
bits : 8 - 16 (9 bit)
access : read-write

UART2_IRQn : UART2_IRQn (Interrupt clear-enable bit)
bits : 9 - 18 (10 bit)
access : read-write

I2C_IRQn : I2C_IRQn (Interrupt clear-enable bit)
bits : 10 - 20 (11 bit)
access : read-write

I2C2_IRQn : I2C2_IRQn (Interrupt clear-enable bit)
bits : 11 - 22 (12 bit)
access : read-write

SPI_IRQn : SPI_IRQn (Interrupt clear-enable bit)
bits : 12 - 24 (13 bit)
access : read-write

SPI2_IRQn : SPI2_IRQn (Interrupt clear-enable bit)
bits : 13 - 26 (14 bit)
access : read-write

ADC_IRQn : ADC_IRQn (Interrupt clear-enable bit)
bits : 14 - 28 (15 bit)
access : read-write

KEYBRD_IRQn : KEYBRD_IRQn (Interrupt clear-enable bit)
bits : 15 - 30 (16 bit)
access : read-write

IRGEN_IRQn : IRGEN_IRQn (Interrupt clear-enable bit)
bits : 16 - 32 (17 bit)
access : read-write

WKUP_GPIO_IRQn : WKUP_GPIO_IRQn (Interrupt clear-enable bit)
bits : 17 - 34 (18 bit)
access : read-write

SWTIM0_IRQn : SWTIM0_IRQn (Interrupt clear-enable bit)
bits : 18 - 36 (19 bit)
access : read-write

SWTIM1_IRQn : SWTIM1_IRQn (Interrupt clear-enable bit)
bits : 19 - 38 (20 bit)
access : read-write

QUADEC_IRQn : QUADEC_IRQn (Interrupt clear-enable bit)
bits : 20 - 40 (21 bit)
access : read-write

USB_IRQn : USB_IRQn (Interrupt clear-enable bit)
bits : 21 - 42 (22 bit)
access : read-write

PCM_IRQn : PCM_IRQn (Interrupt clear-enable bit)
bits : 22 - 44 (23 bit)
access : read-write

SRC_IN_IRQn : SRC_IN_IRQn (Interrupt clear-enable bit)
bits : 23 - 46 (24 bit)
access : read-write

SRC_OUT_IRQn : SRC_OUT_IRQn (Interrupt clear-enable bit)
bits : 24 - 48 (25 bit)
access : read-write

VBUS_IRQn : VBUS_IRQn (Interrupt clear-enable bit)
bits : 25 - 50 (26 bit)
access : read-write

DMA_IRQn : DMA_IRQn (Interrupt clear-enable bit)
bits : 26 - 52 (27 bit)
access : read-write

RF_DIAG_IRQn : RF_DIAG_IRQn (Interrupt clear-enable bit)
bits : 27 - 54 (28 bit)
access : read-write

TRNG_IRQn : TRNG_IRQn (Interrupt clear-enable bit)
bits : 28 - 56 (29 bit)
access : read-write

DCDC_IRQn : DCDC_IRQn (Interrupt clear-enable bit)
bits : 29 - 58 (30 bit)
access : read-write

XTAL16RDY_IRQn : XTAL16RDY_IRQn (Interrupt clear-enable bit)
bits : 30 - 60 (31 bit)
access : read-write

Rsvd__irq__n : Rsvd__irq__n (Reserved)
bits : 31 - 62 (32 bit)
access : read-write



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