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address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Select clock for oscillator calibration
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REF_CLK_SEL : Select clock input for calibration: 0x0 : RC32K 0x1 : RC32M 0x2 : XTAL32K 0x3 : RCX
bits : 0 - 1 (2 bit)
access : read-write
REF_CAL_START : Writing a '1' starts a calibration of the clock selected by CLK_REF_SEL_REG[REF_CLK_SEL]. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready.
bits : 2 - 4 (3 bit)
access : read-write
EXT_CNT_EN_SEL : 0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL. 1 : Enable XTAL_CNT counter from an external input.
bits : 3 - 6 (4 bit)
access : read-write
Count value for oscillator calibration
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REF_CNT_VAL : Indicates the calibration time, with a decrement counter to 1.
bits : 0 - 15 (16 bit)
access : read-write
XTAL32M reference cycles, lower 16 bits
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_CNT_VAL : Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL
bits : 0 - 15 (16 bit)
access : read-only
XTAL32M reference cycles, higher 16 bits
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_CNT_VAL : Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL
bits : 0 - 15 (16 bit)
access : read-only
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