RWBLECNTL_REG

INTSTAT_REG

COEXIFCNTL0_REG

COEXIFCNTL1_REG

BLEMPRIO0_REG

BLEMPRIO1_REG

INTRAWSTAT_REG

INTACK_REG

BASETIMECNT_REG

FINETIMECNT_REG

CNTL2_REG

EM_BASE_REG

DIAGCNTL2_REG

DIAGCNTL3_REG

BDADDRL_REG

BDADDRU_REG

CURRENTRXDESCPTR_REG

DEEPSLCNTL_REG

DEEPSLWKUP_REG

DEEPSLSTAT_REG

ENBPRESET_REG

VERSION_REG

FINECNTCORR_REG

BASETIMECNTCORR_REG

DIAGCNTL_REG

DIAGSTAT_REG

DEBUGADDMAX_REG

DEBUGADDMIN_REG

ERRORTYPESTAT_REG

SWPROFILING_REG

RADIOCNTL0_REG

RADIOCNTL1_REG

RADIOCNTL2_REG

RADIOCNTL3_REG

RWBLECONF_REG

RADIOPWRUPDN_REG

ADVCHMAP_REG

ADVTIM_REG

ACTSCANSTAT_REG

WLPUBADDPTR_REG

WLPRIVADDPTR_REG

WLNBDEV_REG

INTCNTL_REG

AESCNTL_REG

AESKEY31_0_REG

AESKEY63_32_REG

AESKEY95_64_REG

AESKEY127_96_REG

AESPTR_REG

TXMICVAL_REG

RXMICVAL_REG

RFTESTCNTL_REG

RFTESTTXSTAT_REG

RFTESTRXSTAT_REG

TIMGENCNTL_REG

GROSSTIMTGT_REG

FINETIMTGT_REG

SAMPLECLK_REG

SYNCERR : Indicates the maximum number of errors allowed to recognize the synchronization word.
bits : 0 - 2 (3 bit)
access : read-write

RXWINSZDEF : Default Rx Window size in us. Used when device: is master connectedperforms its second receipt.0 is not a valid value. Recommended value is 10 (in decimal).
bits : 4 - 11 (8 bit)
access : read-write

RWBLE_EN : 0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. 1: Enable RW-BLE Core Exchange table pre-fetch mechanism.
bits : 8 - 16 (9 bit)
access : read-write

ADVERTFILT_EN : Advertising Channels Error Filtering Enable control 0: RW-BLE Core reports all errors to RW-BLE Software 1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software
bits : 9 - 18 (10 bit)
access : read-write

HOP_REMAP_DSB : 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled
bits : 16 - 32 (17 bit)
access : read-write

CRC_DSB : 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx.
bits : 17 - 34 (18 bit)
access : read-write

WHIT_DSB : 0: Normal operation. Whitening enabled. 1: Whitening disabled.
bits : 18 - 36 (19 bit)
access : read-write

CRYPT_DSB : 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data.
bits : 19 - 38 (20 bit)
access : read-write

NESN_DSB : 0: Normal operation of Acknowledge 1: Acknowledge scheme disabled: value forced by SW from Tx Descriptorvalue ignored in Rx, where no NESN error reported.
bits : 20 - 40 (21 bit)
access : read-write

SN_DSB : 0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptorvalue ignored in Rx, where no SN error reported.
bits : 21 - 42 (22 bit)
access : read-write

MD_DSB : 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are. value forced by SW from Tx Descriptorvalue just saved in Rx Descriptor during reception
bits : 22 - 44 (23 bit)
access : read-write

SCAN_ABORT : Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 24 - 48 (25 bit)
access : write-only

ADVERT_ABORT : Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 25 - 50 (26 bit)
access : write-only

RFTEST_ABORT : Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested: 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.
bits : 26 - 52 (27 bit)
access : write-only

SWINT_REQ : Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 28 - 56 (29 bit)
access : write-only

REG_SOFT_RST : Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that INT STAT will not be cleared, so the user should also write to BLE_INTACK_REG after the SW Reset
bits : 29 - 58 (30 bit)
access : read-write

MASTER_TGSOFT_RST : Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 30 - 60 (31 bit)
access : write-only

MASTER_SOFT_RST : Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 31 - 62 (32 bit)
access : write-only

CSCNTINTSTAT : Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
bits : 0 - 0 (1 bit)
access : read-only

RXINTSTAT : Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending.
bits : 1 - 2 (2 bit)
access : read-only

SLPINTSTAT : Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
bits : 2 - 4 (3 bit)
access : read-only

EVENTINTSTAT : Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
bits : 3 - 6 (4 bit)
access : read-only

CRYPTINTSTAT : Masked Encryption engine interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
bits : 4 - 8 (5 bit)
access : read-only

ERRORINTSTAT : Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending.
bits : 5 - 10 (6 bit)
access : read-only

GROSSTGTIMINTSTAT : Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 6 - 12 (7 bit)
access : read-only

FINETGTIMINTSTAT : Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
bits : 7 - 14 (8 bit)
access : read-only

EVENTAPFAINTSTAT : End of event / Anticipated Pre-Fetch Abort interrupt status 0: No End of Event interrupt. 1: An End of Event interrupt is pending.
bits : 8 - 16 (9 bit)
access : read-only

SWINTSTAT : SW triggered interrupt status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending
bits : 9 - 18 (10 bit)
access : read-only

COEX_EN : Enable / Disable control of the MWS/WLAN Coexistence control 0: Coexistence interface disabled 1: Coexistence interface enabled
bits : 0 - 0 (1 bit)
access : read-write

SYNCGEN_EN : Determines whether ble_sync is generated or not. 0: ble_sync pulse not generated 1: ble_sync pulse generated
bits : 1 - 2 (2 bit)
access : read-write

WLANRXMSK : Determines how wlan_rx impact BLE Tx and Rx 00: wlan_rx has no impact 01: wlan_rx can stop BLE Tx, no impact on BLE Rx (default mode) 10: wlan_rx can stop BLE Rx, no impact on BLE Tx 11: wlan_rx can stop both BLE Tx and BLE Rx
bits : 4 - 9 (6 bit)
access : read-write

WLANTXMSK : Determines how wlan_tx impact BLE Tx and Rx 00: wlan_tx has no impact (default mode) 01: wlan_tx can stop BLE Tx, no impact on BLE Rx 10: wlan_tx can stop BLE Rx, no impact on BLE Tx 11: wlan_tx can stop both BLE Tx and BLE Rx
bits : 6 - 13 (8 bit)
access : read-write

WLCTXPRIOMODE : Defines Bluetooth Low Energy packet ble_tx mode behavior 00: Tx indication excluding Tx Power up delay 01: Tx indication including Tx Power up delay 10: Tx High priority indicator 11: n/a
bits : 16 - 33 (18 bit)
access : read-write

WLCRXPRIOMODE : Defines Bluetooth Low Energy packet ble_rx mode behavior. 00: Rx indication excluding Rx Power up delay (starts when correlator is enabled) 01: Rx indication including Rx Power up delay 10: Rx High priority indicator 11: n/a
bits : 20 - 41 (22 bit)
access : read-write

WLCPDELAY : Applies on ble_tx if WLCTXPRIOMODE equals 10. Applies on ble_rx if WLCRXPRIOMODE equals 10. Determines the delay (in us) in Tx/Rx enables rises the time Bluetooth Low energy Tx/Rx priority has to be provided .
bits : 0 - 6 (7 bit)
access : read-write

WLCPDURATION : Applies on ble_tx if WLCTXPRIOMODE equals 10 Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines how many s the priority information must be maintained Note that if WLCPDURATION = 0x00, then Tx/Rx priority levels are maintained till Tx/Rx EN are de-asserted.
bits : 8 - 22 (15 bit)
access : read-write

WLCPTXTHR : Applies on ble_tx if WLCTXPRIOMODE equals 10 Determines the threshold for priority setting. If ble_pti[3:0] output value is greater than WLCPTXTHR, then Tx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface
bits : 16 - 36 (21 bit)
access : read-write

WLCPRXTHR : Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines the threshold for Rx priority setting. If ble_pti[3:0] output value is greater than WLCPRXTHR, then Rx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface
bits : 24 - 52 (29 bit)
access : read-write

BLEM0 : Set Priority value for Initiating (Connection Request Response) BLE message
bits : 0 - 3 (4 bit)
access : read-write

BLEM1 : Set Priority value for LLCP BLE message
bits : 4 - 11 (8 bit)
access : read-write

BLEM2 : Set Priority value for Data Channel transmission BLE message
bits : 8 - 19 (12 bit)
access : read-write

BLEM3 : Set Priority value for Initiating (Scanning) BLE message
bits : 12 - 27 (16 bit)
access : read-write

BLEM4 : Set Priority value for Active Scanning BLE message
bits : 16 - 35 (20 bit)
access : read-write

BLEM5 : Set Priority value for Connectable Advertising BLE message
bits : 20 - 43 (24 bit)
access : read-write

BLEM6 : Set Priority value for Non-Connectable Advertising
bits : 24 - 51 (28 bit)
access : read-write

BLEM7 : Set Priority value for Passive Scanning
bits : 28 - 59 (32 bit)
access : read-write

BLEMDEFAULT : Set default priority value for other BLE message than those defined above
bits : 28 - 59 (32 bit)
access : read-write

CSCNTINTRAWSTAT : 625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
bits : 0 - 0 (1 bit)
access : read-only

RXINTRAWSTAT : Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending.
bits : 1 - 2 (2 bit)
access : read-only

SLPINTRAWSTAT : Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
bits : 2 - 4 (3 bit)
access : read-only

EVENTINTRAWSTAT : End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
bits : 3 - 6 (4 bit)
access : read-only

CRYPTINTRAWSTAT : Encryption engine interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
bits : 4 - 8 (5 bit)
access : read-only

ERRORINTRAWSTAT : Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending.
bits : 5 - 10 (6 bit)
access : read-only

GROSSTGTIMINTRAWSTAT : Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 6 - 12 (7 bit)
access : read-only

FINETGTIMINTRAWSTAT : Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
bits : 7 - 14 (8 bit)
access : read-only

EVENTAPFAINTRAWSTAT : End of event / Anticipated Pre-Fetch Abort interrupt raw status 0: No End of Event interrupt. 1: An End of Event interrupt is pending.
bits : 8 - 16 (9 bit)
access : read-only

SWINTRAWSTAT : SW triggered interrupt raw status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending.
bits : 9 - 18 (10 bit)
access : read-only

CSCNTINTACK : 625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed
bits : 0 - 0 (1 bit)
access : write-only

RXINTACK : Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed
bits : 1 - 2 (2 bit)
access : write-only

SLPINTACK : End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed
bits : 2 - 4 (3 bit)
access : write-only

EVENTINTACK : End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed
bits : 3 - 6 (4 bit)
access : write-only

CRYPTINTACK : Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. Resets at 0 when action is performed
bits : 4 - 8 (5 bit)
access : write-only

ERRORINTACK : Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed
bits : 5 - 10 (6 bit)
access : write-only

GROSSTGTIMINTACK : Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. Resets at 0 when action is performed
bits : 6 - 12 (7 bit)
access : write-only

FINETGTIMINTACK : Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. Resets at 0 when action is performed
bits : 7 - 14 (8 bit)
access : write-only

EVENTAPFAINTACK : End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. Resets at 0 when action is performed
bits : 8 - 16 (9 bit)
access : write-only

SWINTACK : SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed
bits : 9 - 18 (10 bit)
access : write-only

BASETIMECNT : Value of the 625us base time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW
bits : 0 - 26 (27 bit)
access : read-only

FINECNT : Value of the current s fine time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration
bits : 0 - 9 (10 bit)
access : read-only

EMACCERRSTAT : Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a 1 at EMACCERRACK bitfield. This bit will be set to 1 by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is 1 then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is 1 .
bits : 0 - 0 (1 bit)
access : read-only

EMACCERRACK : Exchange Memory Access Error Acknowledge. When the SW writes a 1 to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes 0 it will have no affect. The read value is always 0 .
bits : 1 - 2 (2 bit)
access : write-only

EMACCERRMSK : Exchange Memory Access Error Mask: When cleared to 0 the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to 1 an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is 1 .
bits : 2 - 4 (3 bit)
access : read-write

BLE_DIAG_OVR : 1: Overrule BLE_DIAG. 0: BLE_DIAG is not overruled.
bits : 3 - 6 (4 bit)
access : read-write

BLE_CLK_STAT : 0: BLE uses low power clock 1: BLE uses master clock
bits : 6 - 12 (7 bit)
access : read-only

MON_LP_CLK : The SW can only write a 0 to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to 1 . This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc.
bits : 7 - 14 (8 bit)
access : read-only

RADIO_PWRDN_ALLOW : This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to 0 when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted.
bits : 8 - 16 (9 bit)
access : read-only

BLE_CLK_SEL : BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBLECONF_REG[CLK_SEL].
bits : 9 - 23 (15 bit)
access : read-write

BLE_PTI_SOURCE_SEL : 0: Provide to COEX block the PTI value indicated by the Control Structure. Recommended value is 0 . 1: Provide to COEX block the PTI value generated dynamically by the BLE core, which is based on the PTI of the Control Structure.
bits : 17 - 34 (18 bit)
access : read-write

BB_ONLY : Keep to 0.
bits : 18 - 36 (19 bit)
access : read-write

SW_RPL_SPI : Keep to 0.
bits : 19 - 38 (20 bit)
access : read-write

WAKEUPLPSTAT : The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period.
bits : 20 - 40 (21 bit)
access : read-only

BLE_RSSI_SEL : 0: Select Peak-hold RSSI value (default). 1: Select current Average RSSI value.
bits : 21 - 42 (22 bit)
access : read-write

BLE_ARP_PHY_ERR_STAT : When set to 1 then an error occured in BLE ARP sub-block and the BLE_GEN_IRQ will be aserted. It will be set if the ARP_ERROR or PHY_ERROR will be asserted and if the BLE_ARP_ERR_MSK is set to 1 . Writing the value 1 will acknowledge and clear this field.
bits : 22 - 44 (23 bit)
access : read-write

BLE_ARP_ERR_MSK_N : When cleared to 0 then it masks the BLE_ARP_ERR_STAT in order to not trigger a BLE_ERROR_IRQ.
bits : 23 - 46 (24 bit)
access : read-write

BLE_PHY_ERR_MSK_N :
bits : 24 - 48 (25 bit)
access : read-write

BLE_EM_BASE_16_10 : The physical address on the system memory map of the base of the Exchange Memory.
bits : 10 - 26 (17 bit)
access : read-write

DIAG4 : Only relevant when DIAG4_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG4.
bits : 0 - 5 (6 bit)
access : read-write

DIAG4_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 7 - 14 (8 bit)
access : read-write

DIAG5 : Only relevant when DIAG5_EN= 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG5.
bits : 8 - 21 (14 bit)
access : read-write

DIAG5_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 15 - 30 (16 bit)
access : read-write

DIAG6 : Only relevant when DIAG6_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG6.
bits : 16 - 37 (22 bit)
access : read-write

DIAG6_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 23 - 46 (24 bit)
access : read-write

DIAG7 : Only relevant when DIAG7_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG7.
bits : 24 - 53 (30 bit)
access : read-write

DIAG7_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 31 - 62 (32 bit)
access : read-write

DIAG0_BIT : Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port.
bits : 0 - 2 (3 bit)
access : read-write

DIAG0_INV : If set, then the specific diagnostic bit will be inverted.
bits : 3 - 6 (4 bit)
access : read-write

DIAG1_BIT : Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port.
bits : 4 - 10 (7 bit)
access : read-write

DIAG1_INV : If set, then the specific diagnostic bit will be inverted.
bits : 7 - 14 (8 bit)
access : read-write

DIAG2_BIT : Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port.
bits : 8 - 18 (11 bit)
access : read-write

DIAG2_INV : If set, then the specific diagnostic bit will be inverted.
bits : 11 - 22 (12 bit)
access : read-write

DIAG3_BIT : Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port.
bits : 12 - 26 (15 bit)
access : read-write

DIAG3_INV : If set, then the specific diagnostic bit will be inverted.
bits : 15 - 30 (16 bit)
access : read-write

DIAG4_BIT : Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port.
bits : 16 - 34 (19 bit)
access : read-write

DIAG4_INV : If set, then the specific diagnostic bit will be inverted.
bits : 19 - 38 (20 bit)
access : read-write

DIAG5_BIT : Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port.
bits : 20 - 42 (23 bit)
access : read-write

DIAG5_INV : If set, then the specific diagnostic bit will be inverted.
bits : 23 - 46 (24 bit)
access : read-write

DIAG6_BIT : Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port.
bits : 24 - 50 (27 bit)
access : read-write

DIAG6_INV : If set, then the specific diagnostic bit will be inverted.
bits : 27 - 54 (28 bit)
access : read-write

DIAG7_BIT : Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port.
bits : 28 - 58 (31 bit)
access : read-write

DIAG7_INV : If set, then the specific diagnostic bit will be inverted.
bits : 31 - 62 (32 bit)
access : read-write

BDADDRL : Bluetooth Low Energy Device Address. LSB part.
bits : 0 - 31 (32 bit)
access : read-write

BDADDRU : Bluetooth Low Energy Device Address. MSB part.
bits : 0 - 15 (16 bit)
access : read-write

PRIV_NPUB : Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address
bits : 16 - 32 (17 bit)
access : read-write

CURRENTRXDESCPTR : Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List
bits : 0 - 14 (15 bit)
access : read-write

ETPTR : Exchange Table Pointer that determines the starting point of the Exchange Table
bits : 16 - 47 (32 bit)
access : read-write

DEEP_SLEEP_IRQ_EN : Always set to 3 when DEEP_SLEEP_ON is set to 1 . It controls the generation of BLE_WAKEUP_LP_IRQ.
bits : 0 - 1 (2 bit)
access : read-write

DEEP_SLEEP_ON : 0: RW-BLE Core in normal active mode 1: Request RW-BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge.
bits : 2 - 4 (3 bit)
access : write-only

DEEP_SLEEP_CORR_EN : 625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 3 - 6 (4 bit)
access : write-only

SOFT_WAKEUP_REQ : Wake Up Request from RW-BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BLE Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 4 - 8 (5 bit)
access : read-write

DEEP_SLEEP_STAT : Indicator of current Deep Sleep clock mux status: 0: RW-BLE Core is not yet in Deep Sleep Mode 1: RW-BLE Core is in Deep Sleep Mode (only low_power_clk is running)
bits : 15 - 30 (16 bit)
access : read-only

EXTWKUPDSB : External Wake-Up disable 0: RW-BLE Core can be woken by external wake-up 1: RW-BLE Core cannot be woken up by external wake-up
bits : 31 - 62 (32 bit)
access : read-write

DEEPSLTIME : Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz
bits : 0 - 31 (32 bit)
access : read-write

DEEPSLDUR : Actual duration of the last deep sleep phase measured in low_power_clk clock cycle. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low_power_clk clock cycle until the end of the deep sleep phase.
bits : 0 - 31 (32 bit)
access : read-only

TWIRQ_RESET : Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz [0...31.25 ms] for 32.768kHz.
bits : 0 - 9 (10 bit)
access : read-write

TWIRQ_SET : Minimum value is TWIRQ_RESET + 1 . Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
bits : 10 - 30 (21 bit)
access : read-write

TWEXT : Minimum and recommended value is TWIRQ_RESET + 1 . In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
bits : 21 - 52 (32 bit)
access : read-write

BUILD : BLE Core Build Build number.
bits : 0 - 7 (8 bit)
access : read-only

UPG : BLE Core upgrade Upgrade number.
bits : 8 - 23 (16 bit)
access : read-only

REL : BLE Core version Major release number.
bits : 16 - 39 (24 bit)
access : read-only

TYP : BLE Core Type
bits : 24 - 55 (32 bit)
access : read-only

FINECNTCORR : Phase correction value for the 625us reference counter (i.e. Fine Counter) in us.
bits : 0 - 9 (10 bit)
access : read-write

BASETIMECNTCORR : Base Time Counter correction value.
bits : 0 - 26 (27 bit)
access : read-write

DIAG0 : Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG0.
bits : 0 - 5 (6 bit)
access : read-write

DIAG0_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 7 - 14 (8 bit)
access : read-write

DIAG1 : Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG1.
bits : 8 - 21 (14 bit)
access : read-write

DIAG1_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 15 - 30 (16 bit)
access : read-write

DIAG2 : Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG2.
bits : 16 - 37 (22 bit)
access : read-write

DIAG2_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 23 - 46 (24 bit)
access : read-write

DIAG3 : Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG3.
bits : 24 - 53 (30 bit)
access : read-write

DIAG3_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output.
bits : 31 - 62 (32 bit)
access : read-write

DIAG0STAT : Directly connected to ble_dbg0[7:0] output. Debug use only.
bits : 0 - 7 (8 bit)
access : read-only

DIAG1STAT : Directly connected to ble_dbg1[7:0] output. Debug use only.
bits : 8 - 23 (16 bit)
access : read-only

DIAG2STAT : Directly connected to ble_dbg2[7:0] output. Debug use only.
bits : 16 - 39 (24 bit)
access : read-only

DIAG3STAT : Directly connected to ble_dbg3[7:0] output. Debug use only.
bits : 24 - 55 (32 bit)
access : read-only

EM_ADDMAX : Upper limit for the Exchange Memory zone indicated by the em_inzone flag
bits : 0 - 15 (16 bit)
access : read-write

REG_ADDMAX : Upper limit for the Register zone indicated by the reg_inzone flag
bits : 16 - 47 (32 bit)
access : read-write

EM_ADDMIN : Lower limit for the Exchange Memory zone indicated by the em_inzone flag
bits : 0 - 15 (16 bit)
access : read-write

REG_ADDMIN : Lower limit for the Register zone indicated by the reg_inzone flag
bits : 16 - 47 (32 bit)
access : read-write

TXCRYPT_ERROR : Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred
bits : 0 - 0 (1 bit)
access : read-only

RXCRYPT_ERROR : Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred
bits : 1 - 2 (2 bit)
access : read-only

PKTCNTL_EMACC_ERROR : Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred
bits : 2 - 4 (3 bit)
access : read-only

RADIO_EMACC_ERROR : Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. 0: No error 1: Error occurred
bits : 3 - 6 (4 bit)
access : read-only

EVT_SCHDL_EMACC_ERROR : Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 0: No error 1: Error occurred
bits : 4 - 8 (5 bit)
access : read-only

EVT_SCHDL_ENTRY_ERROR : Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred
bits : 5 - 10 (6 bit)
access : read-only

EVT_SCHDL_APFM_ERROR : Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured
bits : 6 - 12 (7 bit)
access : read-only

EVT_CNTL_APFM_ERROR : Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured
bits : 7 - 14 (8 bit)
access : read-only

WHITELIST_ERROR : Indicates White List Timeout error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred
bits : 8 - 16 (9 bit)
access : read-only

IFS_UNDERRUN : Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred
bits : 9 - 18 (10 bit)
access : read-only

ADV_UNDERRUN : Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than the expected value. 0: No error 1: Error occurred
bits : 10 - 20 (11 bit)
access : read-only

LLCHMAP_ERROR : Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred
bits : 11 - 22 (12 bit)
access : read-only

CSFORMAT_ERROR : Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred
bits : 12 - 24 (13 bit)
access : read-only

TXDESC_EMPTY_ERROR : Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. 0: No error 1: Error occurred
bits : 13 - 26 (14 bit)
access : read-only

RXDESC_EMPTY_ERROR : Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. 0: No error 1: Error occurred
bits : 14 - 28 (15 bit)
access : read-only

TXDATA_PTR_ERROR : Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. 0: No error 1: Error occurred
bits : 15 - 30 (16 bit)
access : read-only

RXDATA_PTR_ERROR : Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred
bits : 16 - 32 (17 bit)
access : read-only

CONCEVTIRQ_ERROR : Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software. 0: No error 1: Error occurred
bits : 17 - 34 (18 bit)
access : read-only

SWPROFVAL : Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port
bits : 0 - 31 (32 bit)
access : read-write

XRFSEL : Extended radio selection field, Must be set to 2 .
bits : 16 - 36 (21 bit)
access : read-write

BUSWIDTH : Processor bus width: 1: 32 bits
bits : 0 - 0 (1 bit)
access : read-only

USECRYPT : 1: AES-CCM Encryption block present
bits : 1 - 2 (2 bit)
access : read-only

USEDBG : 1: Diagnostic port instantiated
bits : 2 - 4 (3 bit)
access : read-only

COEX : 1: WLAN Coexistence mechanism present
bits : 3 - 6 (4 bit)
access : read-only

INTMODE : 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement
bits : 4 - 8 (5 bit)
access : read-only

DMMODE : 0: RW-BLE Core is used as a standalone BLE device
bits : 5 - 10 (6 bit)
access : read-only

DECIPHER : 0: AES deciphering not present
bits : 6 - 12 (7 bit)
access : read-only

CLK_SEL : Operating Frequency (in MHz)
bits : 8 - 21 (14 bit)
access : read-only

RFIF : Radio Interface ID
bits : 16 - 38 (23 bit)
access : read-only

ADD_WIDTH : Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary.
bits : 24 - 53 (30 bit)
access : read-only

TXPWRUP : This register holds the length in s of the TX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio.
bits : 0 - 7 (8 bit)
access : read-write

TXPWRDN : This register extends the length in s of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on the selected radio.
bits : 8 - 19 (12 bit)
access : read-write

RXPWRUP : This register holds the length in s of the RX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio.
bits : 16 - 39 (24 bit)
access : read-write

RTRIP_DELAY : Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us
bits : 24 - 54 (31 bit)
access : read-write

ADVCHMAP : Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37.
bits : 0 - 2 (3 bit)
access : read-write

ADVINT : Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in us. Value to program depends on the used Advertising Packet type and the device filtering policy.
bits : 0 - 13 (14 bit)
access : read-write

UPPERLIMIT : Active scan mode upper limit counter value.
bits : 0 - 8 (9 bit)
access : read-only

BACKOFF : Active scan mode back-off counter initialization value.
bits : 16 - 40 (25 bit)
access : read-only

WLPUBADDPTR : Start address pointer of the public devices white list.
bits : 0 - 15 (16 bit)
access : read-write

WLPRIVADDPTR : Start address pointer of the private devices white list.
bits : 0 - 15 (16 bit)
access : read-write

NBPUBDEV : Number of public devices in the white list.
bits : 0 - 7 (8 bit)
access : read-write

NBPRIVDEV : Number of private devices in the white list.
bits : 8 - 23 (16 bit)
access : read-write