\n

Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFE byte (0x0)
mem_usage : registers
protection :

Registers

CHIP_ID1_REG

CHIP_SWC_REG

CHIP_REVISION_REG

CHIP_ID2_REG

CHIP_ID3_REG

CHIP_ID4_REG

CHIP_TEST1_REG

CHIP_TEST2_REG


CHIP_ID1_REG

Chip identification register 1.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID1_REG CHIP_ID1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_ID1

CHIP_ID1 : First character of device type 2632 in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_SWC_REG

Software compatibility register.
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_SWC_REG CHIP_SWC_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_SWC

CHIP_SWC : SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code.
bits : 0 - 3 (4 bit)
access : read-only


CHIP_REVISION_REG

Chip revision register.
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_REVISION_REG CHIP_REVISION_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_REVISION

CHIP_REVISION : Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B'
bits : 0 - 7 (8 bit)
access : read-only


CHIP_ID2_REG

Chip identification register 2.
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID2_REG CHIP_ID2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_ID2

CHIP_ID2 : Second character of device type 2632 in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_ID3_REG

Chip identification register 3.
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID3_REG CHIP_ID3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_ID3

CHIP_ID3 : Third character of device type 2632 in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_ID4_REG

Chip identification register 4.
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID4_REG CHIP_ID4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_ID4

CHIP_ID4 : Fourth character of device type 2632 in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_TEST1_REG

Chip test register 1.
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_TEST1_REG CHIP_TEST1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_LAYOUT_REVISION

CHIP_LAYOUT_REVISION : Chip layout revision, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B'
bits : 0 - 7 (8 bit)
access : read-only


CHIP_TEST2_REG

Chip test register 2.
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_TEST2_REG CHIP_TEST2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_METAL_OPTION

CHIP_METAL_OPTION : Chip metal option value.
bits : 0 - 3 (4 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.