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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_RTCDIV_REG


CLK_RTCDIV_REG

Divisor for RTC 100Hz clock
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RTCDIV_REG CLK_RTCDIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_DIV_FRAC RTC_DIV_INT RTC_DIV_DENOM RTC_DIV_ENABLE RTC_RESET_REQ

RTC_DIV_FRAC : Fractional divisor part for RTC 100Hz generation. if RTC_DIV_DENOM=1, out of 1024 cycles will divide by , the rest is If RTC_DIV_DENOM=0, out of 1000 cycles will divide by , the rest is
bits : 0 - 9 (10 bit)
access : read-write

RTC_DIV_INT : Integer divisor part for RTC 100Hz generation
bits : 10 - 28 (19 bit)
access : read-write

RTC_DIV_DENOM : Selects the denominator for the fractional division: 0b0: 1000 0b1: 1024
bits : 19 - 38 (20 bit)
access : read-write

RTC_DIV_ENABLE : Enable for the 100 Hz generation for the RTC block
bits : 20 - 40 (21 bit)
access : read-write

RTC_RESET_REQ : Reset request for the RTC module
bits : 21 - 42 (22 bit)
access : read-write



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