\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :
Divisor for RTC 100Hz clock
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_DIV_FRAC : Fractional divisor part for RTC 100Hz generation. if RTC_DIV_DENOM=1,
bits : 0 - 9 (10 bit)
access : read-write
RTC_DIV_INT : Integer divisor part for RTC 100Hz generation
bits : 10 - 28 (19 bit)
access : read-write
RTC_DIV_DENOM : Selects the denominator for the fractional division: 0b0: 1000 0b1: 1024
bits : 19 - 38 (20 bit)
access : read-write
RTC_DIV_ENABLE : Enable for the 100 Hz generation for the RTC block
bits : 20 - 40 (21 bit)
access : read-write
RTC_RESET_REQ : Reset request for the RTC module
bits : 21 - 42 (22 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.