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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x56 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_AMBA_REG

PMU_CTRL_REG

SYS_CTRL_REG

SYS_STAT_REG

TRIM_CTRL_REG

RAM_PWR_CTRL_REG

CLK_FREQ_TRIM_REG

CLK_RC32K_REG

CLK_XTAL32K_REG

CLK_RC32M_REG

CLK_RCX_REG

BANDGAP_REG

ANA_STATUS_REG

XTAL32M_START_REG

XTAL32M_TRSTAT_REG

XTALRDY_CTRL_REG

XTALRDY_STAT_REG

XTAL32M_CTRL0_REG

CLK_PER_REG

POR_PIN_REG

POR_TIMER_REG

PMU_SLEEP_REG

POWER_CTRL_REG

POWER_LEVEL_REG

CLK_RADIO_REG

CLK_CTRL_REG


CLK_AMBA_REG

HCLK, PCLK, divider and clock gates
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AMBA_REG CLK_AMBA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_DIV PCLK_DIV OTP_ENABLE

HCLK_DIV : AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 0 - 1 (2 bit)
access : read-write

PCLK_DIV : APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 4 - 9 (6 bit)
access : read-write

OTP_ENABLE : Clock enable for OTP controller
bits : 7 - 14 (8 bit)
access : read-write


PMU_CTRL_REG

Power Management Unit control register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMU_CTRL_REG PMU_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET_ON_WAKEUP TIM_SLEEP RADIO_SLEEP OTP_COPY_DIV MAP_BANDGAP_EN

RESET_ON_WAKEUP : Perform a Hardware Reset after waking up. Booter will be started.
bits : 0 - 0 (1 bit)
access : read-write

TIM_SLEEP : Put PD_TIM in powerdown
bits : 1 - 2 (2 bit)
access : read-write

RADIO_SLEEP : Put the digital part of the radio in powerdown
bits : 2 - 4 (3 bit)
access : read-write

OTP_COPY_DIV : Sets the HCLK division during OTP mirroring
bits : 4 - 9 (6 bit)
access : read-write

MAP_BANDGAP_EN : Enable wakeup diagnostics mapping. When set, these functions are mapped (please set direction to output) P0[2]: BANDGAP_ENABLE P0[1]: Power WOKENUP Note: P0[2] assigned also to SWD_CLK, thus the debugger must be detached before entering into sleep mode with MAP_BANDGAP_EN=1. Refer also to SYS_STAT_REG->DBG_IS_UP.
bits : 6 - 12 (7 bit)
access : read-write


SYS_CTRL_REG

System Control register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CTRL_REG SYS_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP_ADR0 DEV_PHASE OTP_COPY OTPC_RESET_REQ DEBUGGER_ENABLE TIMEOUT_DISABLE SW_RESET

REMAP_ADR0 : Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: RAM (SysRAM1) 0x3: RAM (SysRAM3, 28 kBytes offset) This bitfield only takes affect after a Software Reset.
bits : 0 - 1 (2 bit)
access : read-write

DEV_PHASE : Sets the development phase mode. If this bit is set, in combination with the OTP_COPY bit, the OTP DMA will emulate the OTP mirroring to System RAM. No actual writing to RAM is done, but the exact same amount of time is spend as if the mirroring would take place. This is to mimic the behavior as if the System Code is already in OTP, and the mirroring takes place after waking up, but the (development) code still resides in an external source. If this bit is set to '0' and OTP_COPY='1', then the OTP DMA will actually do the OTP mirroring at wakeup.
bits : 2 - 4 (3 bit)
access : read-write

OTP_COPY : Enables OTP to SysRAM copy action after waking up PD_SYS
bits : 4 - 8 (5 bit)
access : read-write

OTPC_RESET_REQ : Reset request for the OTP controller.
bits : 6 - 12 (7 bit)
access : read-write

DEBUGGER_ENABLE : Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports. 0x0: no debugger enabled. 0x1: SW_CLK = P0[2], SW_DIO=P0[5] 0x2: SW_CLK = P0[2], SW_DIO=P0[1] 0x3: SW_CLK = P0[2], SW_DIO=P0[10]
bits : 7 - 15 (9 bit)
access : read-write

TIMEOUT_DISABLE : Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG.
bits : 10 - 20 (11 bit)
access : read-write

SW_RESET : Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ...
bits : 15 - 30 (16 bit)
access : write-only


SYS_STAT_REG

System status register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_STAT_REG SYS_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAD_IS_DOWN RAD_IS_UP TIM_IS_DOWN TIM_IS_UP DBG_IS_UP XTAL32M_TRIM_READY XTAL32M_SETTLED

RAD_IS_DOWN : Indicates that PD_RAD is in power down
bits : 0 - 0 (1 bit)
access : read-only

RAD_IS_UP : Indicates that PD_RAD is functional
bits : 1 - 2 (2 bit)
access : read-only

TIM_IS_DOWN : Indicates that PD_TIM is in power down
bits : 2 - 4 (3 bit)
access : read-only

TIM_IS_UP : Indicates that PD_TIM is functional
bits : 3 - 6 (4 bit)
access : read-only

DBG_IS_UP : Indicates that the SW debugger is attached and in connection with the ARM.
bits : 4 - 8 (5 bit)
access : read-only

XTAL32M_TRIM_READY : Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG.
bits : 6 - 12 (7 bit)
access : read-only

XTAL32M_SETTLED : Indicates that XTAL32M has had its settle time, as defined by TRIM_CTRL_REG[XTAL_SETTLE_N]
bits : 7 - 14 (8 bit)
access : read-only


TRIM_CTRL_REG

Control trimming of the XTAL32M
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_CTRL_REG TRIM_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_COUNT_N XTAL_TRIM_SELECT XTAL_SETTLE_N

XTAL_COUNT_N : Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 64 cycles. 0x01: 64 0x02: 128 0x3f: 4032
bits : 0 - 5 (6 bit)
access : read-write

XTAL_TRIM_SELECT : Select which source controls the XTAL trimming 0b00: xtal counter. Starts CLK_FREQ_TRIM_REG[XTAL32M_START] after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b01: xtal OK filter. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START], when xtal is ramping is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b11: xtal OK filter, 2 stage. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START] switches to CLK_FREQ_TRIM_REG[XTAL32M_RAMP] after timeout (sw1='1', XTAL32M_CTRL0_REG[XTAL32M_SW_DELAY]), and switches to CLK_FREQ_TRIM_REG[XTAL32M_TRIM] when sw2='1'.
bits : 6 - 13 (8 bit)
access : read-write

XTAL_SETTLE_N : Designates that the XTAL can be safely used as the CPU clock. When XTAL_CLK_CNT reases this value, the signal XTAL32M_SETTLED bit in the SYS_STAT_REG will be set. Counts in steps of 64 xtal clock-cycles.
bits : 8 - 21 (14 bit)
access : read-write


RAM_PWR_CTRL_REG

Control power state of System RAMS
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM_PWR_CTRL_REG RAM_PWR_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM1_PWR_CTRL RAM2_PWR_CTRL RAM3_PWR_CTRL

RAM1_PWR_CTRL : Power state control of the individual RAMs. May only change when the memory isn't accessed. When PD_SYS_IS_UP: 0x0: Normal operation 0x1: Normal operation 0x2: Retained (no access possible) 0x3: Off (memory content corrupted) When PD_MEM_IS_DOWN: 0x0: Retained 0x1: Off (memory content corrupted) 0x2: Retained 0x3: Off (memory content corrupted)
bits : 0 - 1 (2 bit)
access : read-write

RAM2_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 2 - 5 (4 bit)
access : read-write

RAM3_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 4 - 9 (6 bit)
access : read-write


CLK_FREQ_TRIM_REG

Xtal frequency trimming register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_FREQ_TRIM_REG CLK_FREQ_TRIM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL32M_TRIM

XTAL32M_TRIM : Xtal frequency fine trimming register. 0x00: highest frequency 0xFF: lowest frequency
bits : 0 - 7 (8 bit)
access : read-write


CLK_RC32K_REG

32 kHz RC oscillator register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RC32K_REG CLK_RC32K_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC32K_DISABLE RC32K_TRIM

RC32K_DISABLE : Instantly disables the 32kHz RC oscillator Sleep cycles cannot happen with this clock disabled.
bits : 0 - 0 (1 bit)
access : read-write

RC32K_TRIM : 0000 = lowest frequency 0111 = default 1111 = highest frequency
bits : 1 - 5 (5 bit)
access : read-write


CLK_XTAL32K_REG

32 kHz XTAL oscillator register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_XTAL32K_REG CLK_XTAL32K_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL32K_ENABLE XTAL32K_RBIAS XTAL32K_CUR XTAL32K_DISABLE_AMPREG XTAL32K_XTAL1_BIAS_DISABLE

XTAL32K_ENABLE : Enables the 32kHz XTAL oscillator. Also set GP_DATA_REG[P03_P04_FILT_DIS] = 1 for lowest current consumption.
bits : 0 - 0 (1 bit)
access : read-write

XTAL32K_RBIAS : Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog
bits : 1 - 3 (3 bit)
access : read-write

XTAL32K_CUR : Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal
bits : 3 - 9 (7 bit)
access : read-write

XTAL32K_DISABLE_AMPREG : Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock to XTAL32Kp Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km
bits : 7 - 14 (8 bit)
access : read-write

XTAL32K_XTAL1_BIAS_DISABLE :
bits : 8 - 16 (9 bit)
access : read-write


CLK_RC32M_REG

Fast RC control register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RC32M_REG CLK_RC32M_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC32M_DISABLE RC32M_BIAS RC32M_RANGE RC32M_COSC

RC32M_DISABLE : Instantly disables the 32MHz RC oscillator Disabling of the oscillator during sleep happens automatically.
bits : 0 - 0 (1 bit)
access : read-write

RC32M_BIAS : Bias adjustment
bits : 1 - 5 (5 bit)
access : read-write

RC32M_RANGE : Coarse adjust A higher value of RANGE results in a higher frequency, values 2 and 3 are equal
bits : 5 - 11 (7 bit)
access : read-write

RC32M_COSC : C-adjust of RC-oscillator A higher value of COSC results in a lower frequency
bits : 7 - 17 (11 bit)
access : read-write


CLK_RCX_REG

RCX-oscillator control register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RCX_REG CLK_RCX_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCX_ENABLE RCX_RADJUST RCX_CADJUST RCX_C0 RCX_BIAS

RCX_ENABLE : Enable the RCX oscillator
bits : 0 - 0 (1 bit)
access : read-write

RCX_RADJUST : Adjust resistance part of RC-time delay. Lower resistance increases power consumption. 0x0: maximum resistance 0x1: minimum resistance
bits : 1 - 2 (2 bit)
access : read-write

RCX_CADJUST : Adjust capacitance part of RC-time delay. 0x00: minimum capacitance 0x1F: maximum capacitance
bits : 2 - 8 (7 bit)
access : read-write

RCX_C0 : Add unit capacitance to RC-time delay.
bits : 7 - 14 (8 bit)
access : read-write

RCX_BIAS : LDO bias current. 0x0: minimum 0xF: maximum
bits : 8 - 19 (12 bit)
access : read-write


BANDGAP_REG

Bandgap trimming
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BANDGAP_REG BANDGAP_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGR_TRIM BGR_ITRIM

BGR_TRIM : Trim register for bandgap
bits : 0 - 4 (5 bit)
access : read-write

BGR_ITRIM : Current trimming for bias
bits : 5 - 14 (10 bit)
access : read-write


ANA_STATUS_REG

Status bit of analog (power management) circuits
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA_STATUS_REG ANA_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO_CORE_OK LDO_LOW_OK DCDC_OK COMP_VBAT_HIGH_OK COMP_VBAT_HIGH_NOK BANDGAP_OK POR_VBAT_LOW POR_VBAT_HIGH BOOST_SELECTED LDO_XTAL_OK LDO_GPADC_OK FORCE_RUNNING CLKLESS_WAKEUP_STAT

LDO_CORE_OK : Indicates that LDO_CORE output is OK
bits : 0 - 0 (1 bit)
access : read-only

LDO_LOW_OK : Indicates that LDO_LOW output is OK (only valid for high current mode)
bits : 1 - 2 (2 bit)
access : read-only

DCDC_OK : Indicates that VBAT_LOW (buck mode) or VBAT_HIGH (boost mode) is OK
bits : 2 - 4 (3 bit)
access : read-only

COMP_VBAT_HIGH_OK : Indicates that VBAT_HIGH > VBAT_LOW +50 mV
bits : 3 - 6 (4 bit)
access : read-only

COMP_VBAT_HIGH_NOK : Indicates that VBAT_HIGH < VBAT_LOW -50 mV
bits : 4 - 8 (5 bit)
access : read-only

BANDGAP_OK : Indicates that BANDGAP is OK
bits : 5 - 10 (6 bit)
access : read-only

POR_VBAT_LOW : Output of VBAT_LOW supply rail voltage monitoring circuit. 0: Voltage level on VBAT_LOW is lower than POR VBAT_LOW threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_LOW is higher than POR VBAT_LOW threshold VTH_H (rail ok, reset released)
bits : 6 - 12 (7 bit)
access : read-only

POR_VBAT_HIGH : Output of VBAT_HIGH supply rail voltage monitoring circuit. 0: Voltage level on VBAT_HIGH is lower than POR VBAT_HIGH threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_HIGH is higher than POR VBAT_HIGH threshold VTH_H (rail ok, reset released)
bits : 7 - 14 (8 bit)
access : read-only

BOOST_SELECTED : 0: Buck mode detected 1: Boost mode detected
bits : 8 - 16 (9 bit)
access : read-only

LDO_XTAL_OK : Indicates that LDO_XTAL output is OK
bits : 9 - 18 (10 bit)
access : read-only

LDO_GPADC_OK : Indicates that LDO_GPADC output is OK
bits : 10 - 20 (11 bit)
access : read-only

FORCE_RUNNING :
bits : 11 - 22 (12 bit)
access : read-only

CLKLESS_WAKEUP_STAT : Indicates the output of the Clockless wakeup XOR tree. If this signal is '0', the chip will wake up. Use the HIBERN_WKUP_POLARITY bit to set the value to '1' before going into hibernation mode.
bits : 12 - 24 (13 bit)
access : read-only


XTAL32M_START_REG

Trim values for XTAL32M
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL32M_START_REG XTAL32M_START_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL32M_START XTAL32M_RAMP

XTAL32M_START : Xtal frequency trimming register. 0x0 = highest frequency 0xF = lowest frequency.
bits : 0 - 7 (8 bit)
access : read-write

XTAL32M_RAMP : Xtal frequency trimming register. 0x00 : highest frequency 0xFF :lowest frequency
bits : 8 - 23 (16 bit)
access : read-write


XTAL32M_TRSTAT_REG

Read back value of current XTAL trimming
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL32M_TRSTAT_REG XTAL32M_TRSTAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL32M_TRSTAT

XTAL32M_TRSTAT : Reads value of the current XTAL trimming
bits : 0 - 7 (8 bit)
access : read-only


XTALRDY_CTRL_REG

Control register for XTALRDY IRQ
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTALRDY_CTRL_REG XTALRDY_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTALRDY_CNT

XTALRDY_CNT : Number of 32kHz or 256kHz cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. Frequency set by XTALRDY_CLK_SEL. 0x00: no interrupt
bits : 0 - 7 (8 bit)
access : read-write


XTALRDY_STAT_REG


address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTALRDY_STAT_REG XTALRDY_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTALRDY_STAT

XTALRDY_STAT :
bits : 0 - 7 (8 bit)
access : read-only


XTAL32M_CTRL0_REG

Control bits for XTAL32M
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL32M_CTRL0_REG XTAL32M_CTRL0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCBLOCK_ENABLE CORE_AMPL_REG_NULLBIAS CORE_CUR_SET CORE_AMPL_TRIM XTAL32M_SPARE

DCBLOCK_ENABLE : Enable dcblock/high pass filter circuit
bits : 0 - 0 (1 bit)
access : read-write

CORE_AMPL_REG_NULLBIAS : Keep bias in ampl detector alive, even when there is a large drive
bits : 1 - 2 (2 bit)
access : read-write

CORE_CUR_SET : Core current trim setting
bits : 2 - 6 (5 bit)
access : read-write

CORE_AMPL_TRIM : Core amplitude trimming
bits : 5 - 12 (8 bit)
access : read-write

XTAL32M_SPARE :
bits : 8 - 17 (10 bit)
access : read-write


CLK_PER_REG

Peripheral divider register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PER_REG CLK_PER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_DIV TMR_ENABLE WAKEUPCT_ENABLE I2C_ENABLE UART2_ENABLE UART1_ENABLE SPI_ENABLE QUAD_ENABLE

TMR_DIV : Division factor for TIMER0 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 0 - 1 (2 bit)
access : read-write

TMR_ENABLE : Enable TIMER0 and TIMER2 clock
bits : 3 - 6 (4 bit)
access : read-write

WAKEUPCT_ENABLE : Enable Wakeup CaptureTimer clock
bits : 4 - 8 (5 bit)
access : read-write

I2C_ENABLE : Enable I2C clock
bits : 5 - 10 (6 bit)
access : read-write

UART2_ENABLE : Enable UART2 clock
bits : 6 - 12 (7 bit)
access : read-write

UART1_ENABLE : Enable UART1 clock
bits : 7 - 14 (8 bit)
access : read-write

SPI_ENABLE : Enable SPI clock
bits : 10 - 20 (11 bit)
access : read-write

QUAD_ENABLE : Enable the Quadrature clock
bits : 11 - 22 (12 bit)
access : read-write


POR_PIN_REG

Selects a GPIO pin for POR generation
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POR_PIN_REG POR_PIN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_PIN_SELECT POR_PIN_POLARITY

POR_PIN_SELECT : Selects the GPIO which is used for POR generation. 0x0: GPIO pin POReset disabled 0x1: P0_0 0x2: P0_1 ... 0xB: P0_10 0xC: P0_11 0xD - 0xF: reserved
bits : 0 - 3 (4 bit)
access : read-write

POR_PIN_POLARITY : 0: Active Low 1: Active High Note: This applies only for the GPIO pin. Reset pad has a fixed polarity
bits : 7 - 14 (8 bit)
access : read-write


POR_TIMER_REG

Time for POR to happen
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POR_TIMER_REG POR_TIMER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_TIME

POR_TIME : Time for the POReset to happen. Formula: Time = POR_TIME x 4096 x RC32k clock period Default value: ~3 seconds When set to 0x00, the POR TIMER is disabled.
bits : 0 - 6 (7 bit)
access : read-write


PMU_SLEEP_REG

Bandgap refresh interval during sleep
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMU_SLEEP_REG PMU_SLEEP_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BG_REFRESH_INTERVAL

BG_REFRESH_INTERVAL : This is a value defining the interval every which the Bandgap will be activated for refresh. The value represents ticks of rc32k_clk/64 e.g. 30,5 us * 64 = 1,9 ms.
bits : 0 - 11 (12 bit)
access : read-write


POWER_CTRL_REG

Power management control
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER_CTRL_REG POWER_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP_VBAT_HIGH_NOK_ENABLE CMP_VBAT_HIGH_OK_ENABLE VBAT_HL_CONNECT LDO_CORE_RET_ENABLE LDO_CORE_DISABLE LDO_LOW_CTRL_REG LDO_VREF_HOLD_FORCE CP_DISABLE POR_VBAT_LOW_DISABLE POR_VBAT_LOW_HYST_SEL POR_VBAT_LOW_HYST_DIS POR_VBAT_HIGH_DISABLE POR_VBAT_HIGH_HYST_SEL POR_VBAT_HIGH_HYST_DIS VBAT_HL_CONNECT_MODE

CMP_VBAT_HIGH_NOK_ENABLE : Enable cmp_vbat_high_nok
bits : 0 - 0 (1 bit)
access : read-write

CMP_VBAT_HIGH_OK_ENABLE : Enable cmp_vbat_high_ok
bits : 1 - 2 (2 bit)
access : read-write

VBAT_HL_CONNECT : Switch between VBAT_HIGH and VBAT_LOW 0: Open 1: Closed
bits : 2 - 4 (3 bit)
access : read-write

LDO_CORE_RET_ENABLE : LDO_CORE_RETENTION 0: Disabled 1: Enabled
bits : 3 - 6 (4 bit)
access : read-write

LDO_CORE_DISABLE : Disables LDO_CORE
bits : 4 - 8 (5 bit)
access : read-write

LDO_LOW_CTRL_REG : 00: High-current mode in active, LDO_LOW OFF in sleep 01: LDO_LOW OFF 10: Low-current mode in active, Low-current mode in sleep 11: High-current mode in active, Low-current mode in sleep
bits : 5 - 11 (7 bit)
access : read-write

LDO_VREF_HOLD_FORCE : Forces LDO references in HOLD mode
bits : 7 - 14 (8 bit)
access : read-write

CP_DISABLE : Disables LDO_CORE charge-pump circuit
bits : 8 - 16 (9 bit)
access : read-write

POR_VBAT_LOW_DISABLE : Disable por_vbat_low circuit
bits : 9 - 18 (10 bit)
access : read-write

POR_VBAT_LOW_HYST_SEL : 0: Low level selected 1: High level selected
bits : 10 - 20 (11 bit)
access : read-write

POR_VBAT_LOW_HYST_DIS : 0: Hysteresis enabled 1: Hysteresis disabled
bits : 11 - 22 (12 bit)
access : read-write

POR_VBAT_HIGH_DISABLE : Disable por_vbat_high circuit
bits : 12 - 24 (13 bit)
access : read-write

POR_VBAT_HIGH_HYST_SEL : 0: Low level selected 1: High level selected
bits : 13 - 26 (14 bit)
access : read-write

POR_VBAT_HIGH_HYST_DIS : 0: Hysteresis enabled 1: Hysteresis disabled
bits : 14 - 28 (15 bit)
access : read-write

VBAT_HL_CONNECT_MODE : Sets the control mode fo the switch between VBAT_HIGH and VBAT_LOW 0: Manual (default) 1: Automatic (boost mode only)
bits : 15 - 30 (16 bit)
access : read-write


POWER_LEVEL_REG

Power management level and trim settings
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER_LEVEL_REG POWER_LEVEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO_CORE_LEVEL LDO_LOW_TRIM LDO_XTAL_TRIM LDO_CORE_RET_CUR_TRIM DCDC_LEVEL DCDC_TRIM

LDO_CORE_LEVEL : 0: 0.9V 1: 1.0V (testmode, do not use)
bits : 0 - 0 (1 bit)
access : read-write

LDO_LOW_TRIM : Delta from 1.1 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV (coldboot)
bits : 1 - 4 (4 bit)
access : read-write

LDO_XTAL_TRIM : Delta from 0.9 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV
bits : 4 - 10 (7 bit)
access : read-write

LDO_CORE_RET_CUR_TRIM : 00: Default value 01: 2x error amp tail current 10: 2xadaptive bias feedback ratio 11: 2x both tail current and adaptive bias feedback ratio
bits : 7 - 15 (9 bit)
access : read-write

DCDC_LEVEL : 00: 1.1 V 01: 1.8 V (default) 10: 2.5 V 11: 3.0 V
bits : 9 - 19 (11 bit)
access : read-write

DCDC_TRIM : Delta from DCDC_LEVEL nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV
bits : 11 - 24 (14 bit)
access : read-write


CLK_RADIO_REG

Radio PLL control register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RADIO_REG CLK_RADIO_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCU_ENABLE BLE_DIV BLE_LP_RESET BLE_ENABLE

RFCU_ENABLE : Enable the RF control Unit clock
bits : 3 - 6 (4 bit)
access : read-write

BLE_DIV : Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
bits : 4 - 9 (6 bit)
access : read-write

BLE_LP_RESET : Reset for the BLE LP timer
bits : 6 - 12 (7 bit)
access : read-write

BLE_ENABLE : Enable the BLE core clocks
bits : 7 - 14 (8 bit)
access : read-write


CLK_CTRL_REG

Clock control register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CTRL_REG CLK_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_CLK_SEL XTAL32M_DISABLE LP_CLK_SEL RUNNING_AT_LP_CLK RUNNING_AT_RC32M RUNNING_AT_XTAL32M

SYS_CLK_SEL : Selects the clock source. 0x0: XTAL32M (check the XTAL32M_SETTLED and XTAL32M_TRIM_READY bits!!) 0x1: RC32M 0x2/0x3: LP_CL
bits : 0 - 1 (2 bit)
access : read-write

XTAL32M_DISABLE : Setting this bit instantaneously disables the 32 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when RUNNING_AT_XTAL32M is '1' to prevent deadlock. After resetting this bit, wait for XTAL32M_SETTLED or XTAL32M_TRIM_READY to become '1' before switching to XTAL32M clock source.
bits : 2 - 4 (3 bit)
access : read-write

LP_CLK_SEL : Sets the clock source of the LowerPower clock 0x0: RC32K 0x1: RCX 0x2: XTAL32K through the oscillator with an external Crystal. 0x3: XTAL32K through an external square wave generator (set PID of P0[3] to FUNC_GPIO) Change this setting before using this clock, and while RUNNING_AT_LP_CLK == 0.
bits : 3 - 7 (5 bit)
access : read-write

RUNNING_AT_LP_CLK : Indicates that either the LP_CLK is being used as system clock
bits : 5 - 10 (6 bit)
access : read-only

RUNNING_AT_RC32M : Indicates that the RC32M clock is used as clock
bits : 6 - 12 (7 bit)
access : read-only

RUNNING_AT_XTAL32M : Indicates that the XTAL32M clock is used as clock, and may not be switched off
bits : 7 - 14 (8 bit)
access : read-only



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