GP_ADC_CTRL_REG

GP_ADC_RESULT_REG

GP_ADC_PARAM_DIF_REG

GP_ADC_PARAM_SE_REG

GP_ADC_CTRL2_REG

GP_ADC_CTRL3_REG

GP_ADC_OFFP_REG

GP_ADC_OFFN_REG

GP_ADC_TRIM_REG

GP_ADC_CLEAR_INT_REG

GP_ADC_EN : 0: LDO is off and ADC is disabled.. 1: LDO is turned on and afterwards the ADC is enabled.
bits : 0 - 0 (1 bit)
access : read-write

GP_ADC_START : 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero.
bits : 1 - 2 (2 bit)
access : read-write

GP_ADC_CONT : 0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL.
bits : 2 - 4 (3 bit)
access : read-write

GP_ADC_DMA_EN : 0: DMA functionality disabled 1: DMA functionality enabled
bits : 3 - 6 (4 bit)
access : read-write

GP_ADC_INT : 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG.
bits : 4 - 8 (5 bit)
access : read-only

GP_ADC_MINT : 0: Disable (mask) GP_ADC_INT. 1: Enable GP_ADC_INT to ICU.
bits : 5 - 10 (6 bit)
access : read-write

GP_ADC_SE : 0: Differential mode 1: Single ended mode
bits : 6 - 12 (7 bit)
access : read-write

GP_ADC_MUTE : 0: Normal operation 1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC).
bits : 7 - 14 (8 bit)
access : read-write

GP_ADC_SIGN : 0: Default 1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency
bits : 8 - 16 (9 bit)
access : read-write

GP_ADC_CHOP : 0: Chopper mode off 1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements.
bits : 9 - 18 (10 bit)
access : read-write

GP_ADC_LDO_HOLD : 0: GPADC LDO tracking bandgap reference 1: GPADC LDO hold sampled bandgap reference
bits : 10 - 20 (11 bit)
access : read-write

GP_ADC_OFFS_SH_GAIN_SEL :
bits : 11 - 22 (12 bit)
access : read-write

DIE_TEMP_EN : Enables the die-temperature sensor. Output can be measured on GPADC input 4.
bits : 12 - 24 (13 bit)
access : read-write

GP_ADC_VAL : Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits.
bits : 0 - 15 (16 bit)
access : read-only

GP_ADC_ATTN : 0: No attenuator (input voltages up to 0.9V allowed) 1: Enabling 2x attenuator (input voltages up to 1.8V allowed) 2: Enabling 3x attenuator (input voltages up to 2.7V allowed) 3: Enabling 4x attenuator (input voltages up to 3.6V allowed) Enabling the attenuator requires a longer sampling time.
bits : 0 - 1 (2 bit)
access : read-write

GP_ADC_I20U : 1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
bits : 2 - 4 (3 bit)
access : read-write

GP_ADC_OFFS_SH_EN : 0: Disable input shifter 1: Enable input shifter (900mV - 1800mV shifted to 0mV - 900mV)
bits : 3 - 6 (4 bit)
access : read-write

GP_ADC_OFFS_SH_CM : Common mode adjust for offset shifter. Input range is CM +/- 450mV. 0: CM = 1.25V (Input range 0.80 - 1.70) 1: CM = 1.30V (Input range 0.85 - 1.75) (default) 2: CM = 1.35V (Input range 0.90 - 1.80) 3: CM = 1.40V (input range 0.95 - 1.85)
bits : 4 - 9 (6 bit)
access : read-write

GP_ADC_CONV_NRS : 0: 1 sample is taken or 2 in case ADC_CHOP is active. 1: 2 samples are taken. 2: 4 samples are taken. 7: 128 samples are taken.
bits : 6 - 14 (9 bit)
access : read-write

GP_ADC_SMPL_TIME : 0: The sample time (switch is closed) is one ADC_CLK cycle 1: The sample time is 1*8 ADC_CLK cycles 2: The sample time is 2*8 ADC_CLK cycles 15: The sample time is 15*8 ADC_CLK cycles
bits : 9 - 21 (13 bit)
access : read-write

GP_ADC_STORE_DEL : 0: Data is stored after handshake synchronisation 1: Data is stored 2 ADC_CLK cycles after internal start trigger 7: Data is stored 8 ADC_CLK cycles after internal start trigger
bits : 13 - 28 (16 bit)
access : read-write

GP_ADC_EN_DEL : Defines the delay for enabling the ADC after enabling the LDO. 0: Not allowed 1: 4x ADC_CLK period. n: n*4x ADC_CLK period.
bits : 0 - 7 (8 bit)
access : read-write

GP_ADC_INTERVAL : Defines the interval between two ADC conversions in case GP_ADC_CONT is set in units of PER_CLK/1152 (typ 1kHz) 0: No extra delay between two conversions. 1: 1 ms interval between two conversions. 2: 2 ms interval between two conversions. 255: 255 ms interval between two conversions.
bits : 8 - 23 (16 bit)
access : read-write

GP_ADC_OFFP : Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=0 OR GP_ADC_CHOP=1 )
bits : 0 - 9 (10 bit)
access : read-write

GP_ADC_OFFN : Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=1 OR GP_ADC_CHOP=1 )
bits : 0 - 9 (10 bit)
access : read-write

GP_ADC_OFFS_SH_VREF : Offset Shifter common-mode reference fine trimming: 2mV/LSB Default = mid-scale at 1000
bits : 0 - 3 (4 bit)
access : read-write

GP_ADC_LDO_LEVEL : GPADC LDO level 0: 825mV 1: 850mV 2: 875mV 3: 900mV (default) 4: 925mV 5: 950mV 6: 975mV 7:1000mV
bits : 4 - 10 (7 bit)
access : read-write

GP_ADC_CLR_INT : Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0.
bits : 0 - 15 (16 bit)
access : write-only