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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

P0_DATA_REG

P05_MODE_REG

P06_MODE_REG

P07_MODE_REG

P08_MODE_REG

P09_MODE_REG

P010_MODE_REG

P011_MODE_REG

PAD_WEAK_CTRL_REG

P0_SET_DATA_REG

SCAN_OBSERVE_REG

TEST_CTRL_REG

TEST_CTRL2_REG

TEST_CTRL3_REG

TEST_CTRL4_REG

XTAL32M_TESTCTRL0_REG

XTAL32M_TESTCTRL1_REG

BIST_CTRL_REG

ROMBIST_RESULTL_REG

P0_RESET_DATA_REG

ROMBIST_RESULTH_REG

P00_MODE_REG

P01_MODE_REG

P02_MODE_REG

P03_MODE_REG

P04_MODE_REG


P0_DATA_REG

P0 Data input/output Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DATA_REG P0_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_DATA

P0_DATA : Sets P0 output register when written Returns the value of P0 port when read
bits : 0 - 11 (12 bit)
access : read-write


P05_MODE_REG

P05 Mode Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P05_MODE_REG P05_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P06_MODE_REG

P06 Mode Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P06_MODE_REG P06_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P07_MODE_REG

P07 Mode Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P07_MODE_REG P07_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P08_MODE_REG

P08 Mode Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P08_MODE_REG P08_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P09_MODE_REG

P09 Mode Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P09_MODE_REG P09_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P010_MODE_REG

P010 Mode Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P010_MODE_REG P010_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


P011_MODE_REG

P011 Mode Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P011_MODE_REG P011_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write


PAD_WEAK_CTRL_REG

Pad driving strength control Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAD_WEAK_CTRL_REG PAD_WEAK_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_LOW_DRV

PAD_LOW_DRV : 0 = Normal operation 1 = Reduces the driving strength of P0_x pad. Bit x controls the driving strength of P0_x, x=0, 1,..., 11.
bits : 0 - 11 (12 bit)
access : read-write


P0_SET_DATA_REG

P0 Set port pins Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_SET_DATA_REG P0_SET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_SET

P0_SET : Writing a 1 to P0[x] sets P0[x] to 1. Writing 0 is discarded, reading returns 0
bits : 0 - 11 (12 bit)
access : write-only


SCAN_OBSERVE_REG


address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCAN_OBSERVE_REG SCAN_OBSERVE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCAN_FEEDBACK_MUX

SCAN_FEEDBACK_MUX :
bits : 0 - 15 (16 bit)
access : read-only


TEST_CTRL_REG


address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL_REG TEST_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHOW_CLOCKS SHOW_POWER SHOW_DCDC XTAL32M_CAP_TEST_EN LDO_CORE_CAP_BYPASS LDO_CORE_DUMMY_LOAD_ENABLE CP_CAP_BIAS_TRIM ADPLL_SCAN_TEST_EN ADPLL_SCAN_COMP_EN

SHOW_CLOCKS :
bits : 0 - 0 (1 bit)
access : read-write

SHOW_POWER :
bits : 1 - 2 (2 bit)
access : read-write

SHOW_DCDC :
bits : 2 - 4 (3 bit)
access : read-write

XTAL32M_CAP_TEST_EN :
bits : 4 - 8 (5 bit)
access : read-write

LDO_CORE_CAP_BYPASS :
bits : 5 - 10 (6 bit)
access : read-write

LDO_CORE_DUMMY_LOAD_ENABLE :
bits : 6 - 12 (7 bit)
access : read-write

CP_CAP_BIAS_TRIM :
bits : 9 - 19 (11 bit)
access : read-write

ADPLL_SCAN_TEST_EN :
bits : 11 - 22 (12 bit)
access : read-write

ADPLL_SCAN_COMP_EN :
bits : 12 - 24 (13 bit)
access : read-write


TEST_CTRL2_REG


address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL2_REG TEST_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANA_TEST_OUT_SEL ANA_TEST_OUT_TO_PIN ANA_TEST_OUT_PARAM

ANA_TEST_OUT_SEL :
bits : 0 - 9 (10 bit)
access : read-write

ANA_TEST_OUT_TO_PIN :
bits : 11 - 22 (12 bit)
access : read-write

ANA_TEST_OUT_PARAM :
bits : 12 - 27 (16 bit)
access : read-write


TEST_CTRL3_REG


address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL3_REG TEST_CTRL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_TEST_OUT_SEL ENABLE_RFPT RF_TEST_OUT_PARAM RF_TEST_OUT_TO_PIN

RF_TEST_OUT_SEL :
bits : 0 - 5 (6 bit)
access : read-write

ENABLE_RFPT :
bits : 6 - 12 (7 bit)
access : read-write

RF_TEST_OUT_PARAM :
bits : 7 - 19 (13 bit)
access : read-write

RF_TEST_OUT_TO_PIN :
bits : 13 - 26 (14 bit)
access : read-write


TEST_CTRL4_REG


address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL4_REG TEST_CTRL4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_TEST_IN_SEL RF_TEST_IN_PARAM RF_TEST_IN_TO_PIN

RF_TEST_IN_SEL :
bits : 0 - 3 (4 bit)
access : read-write

RF_TEST_IN_PARAM :
bits : 8 - 20 (13 bit)
access : read-write

RF_TEST_IN_TO_PIN :
bits : 13 - 26 (14 bit)
access : read-write


XTAL32M_TESTCTRL0_REG


address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL32M_TESTCTRL0_REG XTAL32M_TESTCTRL0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIKE_FLT_DISABLE OSC_TRIM_OPEN_DISABLE DIFFBUF_BYPASS DCBLOCK_LV_MODE CORE_XTAL_DISCHARGE CORE_MAX_CURRENT CORE_I2V_TO_TESTBUS_10X CORE_I2V_TO_TESTBUS CORE_HOLD_AMP_REG_OVERRIDE CORE_GM_CURRENT CORE_FREQ_TRIM_SW2_AMP BIAS_SAH_HOLD_OVERRIDE

SPIKE_FLT_DISABLE :
bits : 0 - 0 (1 bit)
access : read-write

OSC_TRIM_OPEN_DISABLE :
bits : 1 - 2 (2 bit)
access : read-write

DIFFBUF_BYPASS :
bits : 2 - 4 (3 bit)
access : read-write

DCBLOCK_LV_MODE :
bits : 3 - 6 (4 bit)
access : read-write

CORE_XTAL_DISCHARGE :
bits : 4 - 8 (5 bit)
access : read-write

CORE_MAX_CURRENT :
bits : 5 - 10 (6 bit)
access : read-write

CORE_I2V_TO_TESTBUS_10X :
bits : 6 - 12 (7 bit)
access : read-write

CORE_I2V_TO_TESTBUS :
bits : 7 - 14 (8 bit)
access : read-write

CORE_HOLD_AMP_REG_OVERRIDE :
bits : 8 - 17 (10 bit)
access : read-write

CORE_GM_CURRENT :
bits : 10 - 20 (11 bit)
access : read-write

CORE_FREQ_TRIM_SW2_AMP :
bits : 11 - 24 (14 bit)
access : read-write

BIAS_SAH_HOLD_OVERRIDE :
bits : 14 - 29 (16 bit)
access : read-write


XTAL32M_TESTCTRL1_REG


address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTAL32M_TESTCTRL1_REG XTAL32M_TESTCTRL1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISABLE_TM_CLK LDO_VREF_HOLD_OVERRIDE VARICAP_TEST_ENABLE VARICAP_TEST_SEL_XTAL PROG_VREF_SEL RFCLK_ADPLL_TO_GPIO RFCLK_ADC_TO_GPIO RFCLK_SEL_ADPLL_ADC_TO_GPIO OSC_TRIM_CAP_BIAS

DISABLE_TM_CLK :
bits : 0 - 0 (1 bit)
access : read-write

LDO_VREF_HOLD_OVERRIDE :
bits : 1 - 2 (2 bit)
access : read-write

VARICAP_TEST_ENABLE :
bits : 2 - 4 (3 bit)
access : read-write

VARICAP_TEST_SEL_XTAL :
bits : 3 - 6 (4 bit)
access : read-write

PROG_VREF_SEL :
bits : 4 - 8 (5 bit)
access : read-write

RFCLK_ADPLL_TO_GPIO :
bits : 5 - 10 (6 bit)
access : read-write

RFCLK_ADC_TO_GPIO :
bits : 6 - 12 (7 bit)
access : read-write

RFCLK_SEL_ADPLL_ADC_TO_GPIO :
bits : 7 - 14 (8 bit)
access : read-write

OSC_TRIM_CAP_BIAS :
bits : 8 - 16 (9 bit)
access : read-write


BIST_CTRL_REG


address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIST_CTRL_REG BIST_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM_BIST_CONFIG ROMBIST_ENABLE SYSRAM12_BIST_ENABLE ROM_BIST_BUSY SYSRAM3_BIST_FAIL SYSRAM3_BIST_BUSY SYSRAM12_BIST_FAIL SYSRAM12_BIST_BUSY RAM_BIST_PATTERN SYSRAM3_BIST_ENABLE

RAM_BIST_CONFIG :
bits : 0 - 1 (2 bit)
access : read-write

ROMBIST_ENABLE :
bits : 2 - 4 (3 bit)
access : read-write

SYSRAM12_BIST_ENABLE :
bits : 3 - 6 (4 bit)
access : read-write

ROM_BIST_BUSY :
bits : 5 - 10 (6 bit)
access : read-only

SYSRAM3_BIST_FAIL :
bits : 7 - 14 (8 bit)
access : read-only

SYSRAM3_BIST_BUSY :
bits : 8 - 16 (9 bit)
access : read-only

SYSRAM12_BIST_FAIL :
bits : 10 - 20 (11 bit)
access : read-only

SYSRAM12_BIST_BUSY :
bits : 11 - 22 (12 bit)
access : read-only

RAM_BIST_PATTERN :
bits : 12 - 25 (14 bit)
access : read-write

SYSRAM3_BIST_ENABLE :
bits : 14 - 28 (15 bit)
access : read-write


ROMBIST_RESULTL_REG


address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROMBIST_RESULTL_REG ROMBIST_RESULTL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROMBIST_RESULTL

ROMBIST_RESULTL :
bits : 0 - 15 (16 bit)
access : read-only


P0_RESET_DATA_REG

P0 Reset port pins Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_RESET_DATA_REG P0_RESET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_RESET

P0_RESET : Writing a 1 to P0[x] sets P0[x] to 0. Writing 0 is discarded, reading returns 0.
bits : 0 - 11 (12 bit)
access : write-only


ROMBIST_RESULTH_REG


address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROMBIST_RESULTH_REG ROMBIST_RESULTH_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROMBIST_RESULTH

ROMBIST_RESULTH :
bits : 0 - 15 (16 bit)
access : read-only


P00_MODE_REG

P00 Mode Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P00_MODE_REG P00_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = GPIO (pin direction determined by PUPD field) 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SYS_CLK 6 = LP_CLK 7 = Reserved 8 = Reserved 9 = I2C_SCL 10 = I2C_SDA 11 = PWM5 12 = PWM6 13 = PWM7 14 = Reserved 15 = ADC (only for P0_1, P0_2, P0_6 and P0_7) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (signals mapped to P0[3:0] are also mapped to P0[11:8]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = Reserved 22 = Reserved 23 = PWM2 24 = PWM3 25 = PWM4 26 = SPI_DI 27 = SPI_DO 28 = SPI_CLK 29 = SPI_CSN0 30 = SPI_CSN1 31 = Reserved Note: When a certain input function (like SPI_DI) is selected on more than 1 pins, the pin of the lowest index has the highest priority.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P01_MODE_REG

P01 Mode Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P01_MODE_REG P01_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P02_MODE_REG

P02 Mode Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P02_MODE_REG P02_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P03_MODE_REG

P03 Mode Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P03_MODE_REG P03_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P04_MODE_REG

P04 Mode Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P04_MODE_REG P04_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P00_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected
bits : 8 - 17 (10 bit)
access : read-write



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