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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection :

Registers

GPIO_IRQ0_IN_SEL_REG

GPIO_INT_LEVEL_CTRL_REG

IRQ_IN_SEL0_REG

CTRL_REG

GPIO_IRQ1_IN_SEL_REG

GPIO_IRQ2_IN_SEL_REG

GPIO_IRQ3_IN_SEL_REG

GPIO_IRQ4_IN_SEL_REG

GPIO_DEBOUNCE_REG

GPIO_RESET_IRQ_REG


GPIO_IRQ0_IN_SEL_REG

GPIO interrupt selection for GPIO_IRQ0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IRQ0_IN_SEL_REG GPIO_IRQ0_IN_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_IRQ0_SEL

KBRD_IRQ0_SEL : input selection that can generate a GPIO interrupt 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P0[8] is selected 10: P0[9] is selected 11: P0[10] is selected 12: P0[11] is selected all others: no input selected
bits : 0 - 3 (4 bit)
access : read-write


GPIO_INT_LEVEL_CTRL_REG

high or low level select for GPIO interrupts
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_INT_LEVEL_CTRL_REG GPIO_INT_LEVEL_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUT_LEVEL0 INPUT_LEVEL1 INPUT_LEVEL2 INPUT_LEVEL3 INPUT_LEVEL4 EDGE_LEVELn0 EDGE_LEVELn1 EDGE_LEVELn2 EDGE_LEVELn3 EDGE_LEVELn4

INPUT_LEVEL0 : 0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low.
bits : 0 - 0 (1 bit)
access : read-write

INPUT_LEVEL1 : see INPUT_LEVEL0, but for GPIO IRQ1
bits : 1 - 2 (2 bit)
access : read-write

INPUT_LEVEL2 : see INPUT_LEVEL0, but for GPIO IRQ2
bits : 2 - 4 (3 bit)
access : read-write

INPUT_LEVEL3 : see INPUT_LEVEL0, but for GPIO IRQ3
bits : 3 - 6 (4 bit)
access : read-write

INPUT_LEVEL4 : see INPUT_LEVEL0, but for GPIO IRQ4
bits : 4 - 8 (5 bit)
access : read-write

EDGE_LEVELn0 : 0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0
bits : 5 - 10 (6 bit)
access : read-write

EDGE_LEVELn1 : see EDGE_LEVELn0, but for GPIO IRQ1
bits : 6 - 12 (7 bit)
access : read-write

EDGE_LEVELn2 : see EDGE_LEVELn0, but for GPIO IRQ2
bits : 7 - 14 (8 bit)
access : read-write

EDGE_LEVELn3 : see EDGE_LEVELn0, but for GPIO IRQ3
bits : 8 - 16 (9 bit)
access : read-write

EDGE_LEVELn4 : see EDGE_LEVELn0, but for GPIO IRQ4
bits : 9 - 18 (10 bit)
access : read-write


IRQ_IN_SEL0_REG

GPIO interrupt selection for KBRD_IRQ for P0
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_IN_SEL0_REG IRQ_IN_SEL0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_P00_EN KBRD_P01_EN KBRD_P02_EN KBRD_P03_EN KBRD_P04_EN KBRD_P05_EN KBRD_P06_EN KBRD_P07_EN KBRD_P08_EN KBRD_P09_EN KBRD_P10_EN KBRD_P11_EN

KBRD_P00_EN : enable P0[0] for the keyboard interrupt
bits : 0 - 0 (1 bit)
access : read-write

KBRD_P01_EN : enable P0[1] for the keyboard interrupt
bits : 1 - 2 (2 bit)
access : read-write

KBRD_P02_EN : enable P0[2] for the keyboard interrupt
bits : 2 - 4 (3 bit)
access : read-write

KBRD_P03_EN : enable P0[3] for the keyboard interrupt
bits : 3 - 6 (4 bit)
access : read-write

KBRD_P04_EN : enable P0[4] for the keyboard interrupt
bits : 4 - 8 (5 bit)
access : read-write

KBRD_P05_EN : enable P0[5] for the keyboard interrupt
bits : 5 - 10 (6 bit)
access : read-write

KBRD_P06_EN : enable P0[6] for the keyboard interrupt
bits : 6 - 12 (7 bit)
access : read-write

KBRD_P07_EN : enable P0[7] for the keyboard interrupt
bits : 7 - 14 (8 bit)
access : read-write

KBRD_P08_EN : enable P0[8] for the keyboard interrupt
bits : 8 - 16 (9 bit)
access : read-write

KBRD_P09_EN : enable P0[9] for the keyboard interrupt
bits : 9 - 18 (10 bit)
access : read-write

KBRD_P10_EN : enable P0[10] for the keyboard interrupt
bits : 10 - 20 (11 bit)
access : read-write

KBRD_P11_EN : enable P0[11] for the keyboard interrupt
bits : 11 - 22 (12 bit)
access : read-write


CTRL_REG

GPIO Kbrd control register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_REG CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY_REPEAT KBRD_LEVEL KBRD_REL

KEY_REPEAT : While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer.
bits : 0 - 5 (6 bit)
access : read-write

KBRD_LEVEL : 0 = enabled input will generate KBRD IRQ if that input is high. 1 = enabled input will generate KBRD IRQ if that input is low.
bits : 6 - 12 (7 bit)
access : read-write

KBRD_REL : 0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled)
bits : 7 - 14 (8 bit)
access : read-write


GPIO_IRQ1_IN_SEL_REG

GPIO interrupt selection for GPIO_IRQ1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IRQ1_IN_SEL_REG GPIO_IRQ1_IN_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_IRQ1_SEL

KBRD_IRQ1_SEL : see KBRD_IRQ0_SEL
bits : 0 - 3 (4 bit)
access : read-write


GPIO_IRQ2_IN_SEL_REG

GPIO interrupt selection for GPIO_IRQ2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IRQ2_IN_SEL_REG GPIO_IRQ2_IN_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_IRQ2_SEL

KBRD_IRQ2_SEL : see KBRD_IRQ0_SEL
bits : 0 - 3 (4 bit)
access : read-write


GPIO_IRQ3_IN_SEL_REG

GPIO interrupt selection for GPIO_IRQ3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IRQ3_IN_SEL_REG GPIO_IRQ3_IN_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_IRQ3_SEL

KBRD_IRQ3_SEL : see KBRD_IRQ0_SEL
bits : 0 - 3 (4 bit)
access : read-write


GPIO_IRQ4_IN_SEL_REG

GPIO interrupt selection for GPIO_IRQ4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IRQ4_IN_SEL_REG GPIO_IRQ4_IN_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KBRD_IRQ4_SEL

KBRD_IRQ4_SEL : see KBRD_IRQ0_SEL
bits : 0 - 3 (4 bit)
access : read-write


GPIO_DEBOUNCE_REG

debounce counter value for GPIO inputs
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_DEBOUNCE_REG GPIO_DEBOUNCE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEB_VALUE DEB_ENABLE0 DEB_ENABLE1 DEB_ENABLE2 DEB_ENABLE3 DEB_ENABLE4 DEB_ENABLE_KBRD

DEB_VALUE : Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63
bits : 0 - 5 (6 bit)
access : read-write

DEB_ENABLE0 : enables the debounce counter for GPIO IRQ0
bits : 6 - 12 (7 bit)
access : read-write

DEB_ENABLE1 : enables the debounce counter for GPIO IRQ1
bits : 7 - 14 (8 bit)
access : read-write

DEB_ENABLE2 : enables the debounce counter for GPIO IRQ2
bits : 8 - 16 (9 bit)
access : read-write

DEB_ENABLE3 : enables the debounce counter for GPIO IRQ3
bits : 9 - 18 (10 bit)
access : read-write

DEB_ENABLE4 : enables the debounce counter for GPIO IRQ4
bits : 10 - 20 (11 bit)
access : read-write

DEB_ENABLE_KBRD : enables the debounce counter for the KBRD interface
bits : 11 - 22 (12 bit)
access : read-write


GPIO_RESET_IRQ_REG

GPIO interrupt reset register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_RESET_IRQ_REG GPIO_RESET_IRQ_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET_GPIO0_IRQ RESET_GPIO1_IRQ RESET_GPIO2_IRQ RESET_GPIO3_IRQ RESET_GPIO4_IRQ RESET_KBRD_IRQ

RESET_GPIO0_IRQ : writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0.
bits : 0 - 0 (1 bit)
access : write-only

RESET_GPIO1_IRQ : writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0.
bits : 1 - 2 (2 bit)
access : write-only

RESET_GPIO2_IRQ : writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0.
bits : 2 - 4 (3 bit)
access : write-only

RESET_GPIO3_IRQ : writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0.
bits : 3 - 6 (4 bit)
access : write-only

RESET_GPIO4_IRQ : writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0.
bits : 4 - 8 (5 bit)
access : write-only

RESET_KBRD_IRQ : writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0.
bits : 5 - 10 (6 bit)
access : write-only



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