MODE_REG

TIM1_REG

TIM2_REG

AHBADR_REG

CELADR_REG

NWORDS_REG

STAT_REG

PADDR_REG

PWORD_REG

OTPC_MODE_MODE : Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 0x0: DSTBY. The OTP memory is in deep standby mode (power supply ON and internal LDO OFF). 0x1: STBY. The OTP memory is powered (power supply ON and internal LDO ON, but is not selected). 0x2: READ. The OTP memory is in the normal read mode. 0x3: PROG. The OTP memory is in programming mode. 0x4: PVFY. The OTP memory is in programming verification mode (margin read after programming). 0x5: RINI. The OTP memory is in initial read mode (initial margin read). 0x6: AREAD. Copying of data from the OTP memory to a system RAM by using the internal DMA. See also the registers OTPC_AHBADR_REG, OTPC_CELADR_REG and OTPC_NWORDS_REG. Whenever the OTPC_MODE_REG[MODE] is changing, the status bit OTPC_STAT_REG[OTPC_STAT_MRDY] gets the value zero. The new mode will be ready for use when the OTPC_STAT_MRDY become again 1. During the mode transition the OTPC_MODE_REG[MODE] become read only. Do not try to use or change any function of the controller until the OTPC_STAT_MRDY bit to become equal to 1. The data transferring that is performed by using the AREAD mode is completed when OTPC_STAT_MRDY becomes again 1. The mode change automatically to DSTBY with the completion of the transfer.
bits : 0 - 2 (3 bit)
access : read-write

OTPC_MODE_USE_TST_ROW : Selects the memory area of the OTP cell that will be used. 0 - Uses the main memory area of the OTP cell 1 - Uses the test row of the OTP cell The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next programming or reading mode that will be enabled.
bits : 4 - 8 (5 bit)
access : read-write

OTPC_MODE_HT_MARG_EN : Defines the temperature condition under which is performed a margin read. It affects only the initial margin read (RINI mode) and the programming verification margin read (PVFY). 0 : Regular temperature condition (less than 85°C) 1 : High temperature condition (85°C or more) The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next PVFY or RINI mode that will be enabled. The READ mode is not affected by the setting of this configuration bit.
bits : 5 - 10 (6 bit)
access : read-write

OTPC_MODE_PRG_SEL : Defines the part of the OTP cell that is programmed by the controller during the PROG mode, for each program request that is applied. 0x0 : Both normal and redundancy arrays are programmed. This is the normal way of programming. 0x1 : Only the normal array is programmed. 0x2 : Only the redundancy array is programmed. 0x3 : Reserved The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The setting will take effect when will be enabled again the PROG mode.
bits : 6 - 13 (8 bit)
access : read-write

OTPC_TIM1_CC_T_1US : The number of hclk_c clock periods (minus one) that give a time interval equal to 1us. This setting affects all the timing parameters that refer to microseconds, due to that defines the correspondence of a microsecond to a number of hclk_c clock cycles.
bits : 0 - 6 (7 bit)
access : read-write

OTPC_TIM1_CC_T_20NS : The number of hclk_c clock periods (minus one) that give a time interval that is at least higher than 20 ns.
bits : 8 - 17 (10 bit)
access : read-write

OTPC_TIM1_CC_T_RD : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns. This timing parameter refers to the access time of the OTP memory.
bits : 12 - 26 (15 bit)
access : read-write

OTPC_TIM1_US_T_PL : The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP. It must be at least 10us.
bits : 16 - 35 (20 bit)
access : read-write

OTPC_TIM1_US_T_CS : The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for any kind of read. It must be at least 10us.
bits : 20 - 43 (24 bit)
access : read-write

OTPC_TIM1_US_T_CSP : The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for programming. It must be : - at least 10us - no more than 100us
bits : 24 - 54 (31 bit)
access : read-write

OTPC_TIM2_US_T_PW : The number of microseconds (minus one) that lasts the programming of each bit. It must be : - at least 10us - no more than 20us
bits : 0 - 4 (5 bit)
access : read-write

OTPC_TIM2_US_T_PWI : The number of microseconds (minus one) between two consecutive programming pulses. It must be : - at least 1us - no more than 5us
bits : 5 - 12 (8 bit)
access : read-write

OTPC_TIM2_US_T_PPR : The number of microseconds (minus one) for recovery after a programming sequence. It must be : - at least 5us - no more than 100us
bits : 8 - 22 (15 bit)
access : read-write

OTPC_TIM2_US_T_PPS : The number of microseconds (minus one) that are required after the enabling of the programming in the OTP memory and before to be applied the first programming pulse. It must be : - at least 5us - no more than 20us
bits : 16 - 36 (21 bit)
access : read-write

OTPC_TIM2_US_T_VDS : The number of microseconds (minus one) that are required after the enabling of the power supply of the OTP memory and before to become ready for the enabling of the internal LDO. It must be at least 1us.
bits : 21 - 44 (24 bit)
access : read-write

OTPC_TIM2_US_T_PPH : The number of microseconds (minus one) that are required after the last programming pulse and before to be disabled the programming mode in the OTP memory. It must be: - at least 5us - no more than 20us
bits : 24 - 52 (29 bit)
access : read-write

OTPC_TIM2_US_T_SAS : The number of microseconds (minus one) that are required after the exit from the deep sleep standby mode and before to become ready to enter in an active mode (reading or programming). It must be at least 2us.
bits : 29 - 59 (31 bit)
access : read-write

OTPC_TIM2_US_ADD_CC_EN : Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds. 0 : The extra hclk_c clock cycle is not applied 1 : The extra hclk_c clock cycle is applied
bits : 31 - 62 (32 bit)
access : read-write

OTPC_AHBADR : It is the AHB address used by the AHB master interface of the controller (the bits [15:2]). The bits [1:0] of the address are considered always as equal to zero. The value of the register remains unchanged, by the internal logic of the controller.
bits : 2 - 17 (16 bit)
access : read-write

OTPC_CELADR : Defines a word address inside the OTP cell that will be used during the AREAD mode and the OTP mirroring.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_NWORDS : The number of words (minus one) that will be copied by the AREAD mode. During mirroring, this register reflects the amount of data that will be copied.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_STAT_PRDY : Indicates the state of the programming process. 0: The controller is busy. A programming is in progress. 1: The logic which performs programming is idle.
bits : 0 - 0 (1 bit)
access : read-only

OTPC_STAT_PBUF_EMPTY : Indicates the status of the programming buffer (PBUF). 0 : The PBUF contains the address and the data of a programming request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should not be written as long as this status bit is zero. 1 : The PBUF is empty and a new programming request can be registered in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG registers. This status bit gets the value zero every time where a programming is triggered by the OTPC_PADDR_REG (only if the PROG mode is active).
bits : 1 - 2 (2 bit)
access : read-only

OTPC_STAT_MRDY : Indicates the progress of the transition from a mode of operation to a new mode of operation. 0 : There is a transition in progress in a new mode of operation . Wait until the transition to be completed. 1 : The transition to the new mode of operation has been completed. The function that has been enabled by the new mode can be used. A new mode can be applied. This status bit gets the value zero every time where the OTPC_MODE_REG[MODE] is changing. Do not try to use or change any function of the controller until this status bit to become equal to 1.
bits : 2 - 4 (3 bit)
access : read-only

OTPC_PADDR : The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTPC_PADDR_REG refers to a word address. The OTPC_PADDR_REG has to be writen after the OTP_PWORD_REG and only if the OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0). A writting to the OTPC_PADDR_REG triggers the controller to start the programming procedure (only if the PROG mode is active).
bits : 0 - 12 (13 bit)
access : read-write

OTPC_PWORD : The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP memory, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTP_PWORD_REG must be written before the OTPC_PADDR_REG and only if OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] = 1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0).
bits : 0 - 31 (32 bit)
access : read-write