\n
address_offset : 0x0 Bytes (0x0)
size : 0xBC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFF_POLARITY :
bits : 3 - 6 (4 bit)
access : read-write
RF_BIAS :
bits : 8 - 19 (12 bit)
access : read-write
TIA_BIAS :
bits : 12 - 24 (13 bit)
access : read-write
PA_POWER_SETTING :
bits : 24 - 51 (28 bit)
access : read-write
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_EXT_LUT :
bits : 0 - 9 (10 bit)
access : read-write
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALSTATE :
bits : 0 - 3 (4 bit)
access : read-only
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO_CAL :
bits : 0 - 0 (1 bit)
access : write-only
EO_CAL :
bits : 1 - 2 (2 bit)
access : read-only
RF_CAL_CTRL_SPARE :
bits : 2 - 4 (3 bit)
access : read-write
DC_OFFSET_CAL_DIS :
bits : 4 - 8 (5 bit)
access : read-write
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EO_CAL_CLEAR :
bits : 0 - 0 (1 bit)
access : write-only
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OFFP_I_RD :
bits : 0 - 8 (9 bit)
access : read-only
ADC_OFFN_I_RD :
bits : 9 - 26 (18 bit)
access : read-only
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OFFP_Q_RD :
bits : 0 - 8 (9 bit)
access : read-only
ADC_OFFN_Q_RD :
bits : 9 - 26 (18 bit)
access : read-only
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF_SPARE_BITS :
bits : 0 - 15 (16 bit)
access : read-write
RF_SPARE_BITS_HV :
bits : 16 - 39 (24 bit)
access : read-write
RF_SPARE_IN :
bits : 24 - 51 (28 bit)
access : read-only
RF_SPARE_IN_EN :
bits : 28 - 56 (29 bit)
access : read-write
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_CAL_TRIM :
bits : 0 - 1 (2 bit)
access : read-write
IF_MUTE :
bits : 4 - 8 (5 bit)
access : read-write
IFF_DCOC_DAC_DIS :
bits : 5 - 10 (6 bit)
access : read-write
RF_IFF_CTRL_SPARE :
bits : 6 - 17 (12 bit)
access : read-write
IFF_COMPLEX_DIS :
bits : 12 - 24 (13 bit)
access : read-write
IFF_DCOC_DAC_REFCUR_CTRL :
bits : 13 - 27 (15 bit)
access : read-write
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_LDO_EN :
bits : 0 - 0 (1 bit)
access : read-write
RADIO_LDO_EN_SEL :
bits : 1 - 2 (2 bit)
access : read-write
RADIO_LDO_EN_WR :
bits : 2 - 4 (3 bit)
access : read-write
ADPLLDIG_PWR_SW1_EN :
bits : 3 - 6 (4 bit)
access : read-write
ADPLLDIG_LDO_EN_SEL :
bits : 4 - 8 (5 bit)
access : read-write
ADPLLDIG_LDO_EN_WR :
bits : 5 - 10 (6 bit)
access : read-write
ADPLLDIG_HRESET_N :
bits : 8 - 16 (9 bit)
access : read-write
ADPLLDIG_HCLK_EN :
bits : 9 - 18 (10 bit)
access : read-write
RADIO_REGS_RDY :
bits : 16 - 32 (17 bit)
access : read-write
ADPLLDIG_HCLK_DIS :
bits : 17 - 34 (18 bit)
access : read-write
RADIO_INIT_AUTOCLEAR :
bits : 24 - 48 (25 bit)
access : read-write
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_DC_OFFSET_SEL :
bits : 0 - 0 (1 bit)
access : read-write
ADC_MUTE :
bits : 13 - 26 (14 bit)
access : read-write
ADC_SIGN :
bits : 14 - 28 (15 bit)
access : read-write
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OFFP_I_WR :
bits : 0 - 8 (9 bit)
access : read-write
ADC_OFFN_I_WR :
bits : 9 - 26 (18 bit)
access : read-write
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_OFFP_Q_WR :
bits : 0 - 8 (9 bit)
access : read-write
ADC_OFFN_Q_WR :
bits : 9 - 26 (18 bit)
access : read-write
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM_DUTY_POS :
bits : 0 - 2 (3 bit)
access : read-write
TRIM_DUTY_NEG :
bits : 3 - 8 (6 bit)
access : read-write
PA_RAMP_STEP_SPEED :
bits : 8 - 17 (10 bit)
access : read-write
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF_LDO_RADIO_VREF_SEL :
bits : 0 - 0 (1 bit)
access : read-write
RF_LDO_DTC_VREF_SEL :
bits : 1 - 2 (2 bit)
access : read-write
RF_LDO_DCO_VREF_SEL :
bits : 2 - 4 (3 bit)
access : read-write
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIXER_IP2_DAC_I_TRIM :
bits : 0 - 8 (9 bit)
access : read-write
MIXER_IP2_DAC_Q_TRIM :
bits : 16 - 40 (25 bit)
access : read-write
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIX_CAL_CAP_WR_1M :
bits : 0 - 3 (4 bit)
access : read-write
MIX_CAL_CAP_WR_2M :
bits : 8 - 19 (12 bit)
access : read-write
MIX_CAL_SELECT :
bits : 16 - 32 (17 bit)
access : read-write
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFIO_TUNE_CAP_TRIM_RX :
bits : 0 - 3 (4 bit)
access : read-write
RFIO_TUNE_CAP_TRIM_TX :
bits : 8 - 19 (12 bit)
access : read-write
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_GAIN0_HP :
bits : 0 - 4 (5 bit)
access : read-write
LNA_TRIM_GAIN1_HP :
bits : 5 - 14 (10 bit)
access : read-write
LNA_TRIM_GAIN2_HP :
bits : 10 - 24 (15 bit)
access : read-write
LNA_TRIM_GAIN3_HP :
bits : 15 - 34 (20 bit)
access : read-write
LNA_TRIM_GAIN4_HP :
bits : 20 - 44 (25 bit)
access : read-write
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_GAIN0_LP :
bits : 0 - 4 (5 bit)
access : read-write
LNA_TRIM_GAIN1_LP :
bits : 5 - 14 (10 bit)
access : read-write
LNA_TRIM_GAIN2_LP :
bits : 10 - 24 (15 bit)
access : read-write
LNA_TRIM_GAIN3_LP :
bits : 15 - 34 (20 bit)
access : read-write
LNA_TRIM_GAIN4_LP :
bits : 20 - 44 (25 bit)
access : read-write
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_LDO_EN_RD :
bits : 0 - 0 (1 bit)
access : read-only
RADIO_LDO_ZERO_EN_RD :
bits : 1 - 2 (2 bit)
access : read-only
ADPLLDIG_LDO_EN_RD :
bits : 2 - 4 (3 bit)
access : read-only
ADPLLDIG_LDO_ZERO_EN_RD :
bits : 3 - 6 (4 bit)
access : read-only
ldo_dco_en_rd :
bits : 4 - 8 (5 bit)
access : read-only
ldo_dtc_en_rd :
bits : 5 - 10 (6 bit)
access : read-only
ldo_radio_vref_hold_rd :
bits : 6 - 12 (7 bit)
access : read-only
ldo_dco_vref_hold_rd :
bits : 7 - 14 (8 bit)
access : read-only
ldo_dtc_vref_hold_rd :
bits : 8 - 16 (9 bit)
access : read-only
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_CASC :
bits : 0 - 2 (3 bit)
access : read-write
LNA_MODE_GAIN0_LP :
bits : 4 - 9 (6 bit)
access : read-write
LNA_MODE_GAIN1_LP :
bits : 8 - 17 (10 bit)
access : read-write
LNA_MODE_GAIN2_LP :
bits : 12 - 25 (14 bit)
access : read-write
LNA_MODE_GAIN3_LP :
bits : 16 - 33 (18 bit)
access : read-write
LNA_MODE_GAIN4_LP :
bits : 20 - 41 (22 bit)
access : read-write
LNA_SPARE :
bits : 24 - 49 (26 bit)
access : read-write
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADPLLDIG_SYNC_CLK_INV :
bits : 0 - 0 (1 bit)
access : read-write
ADPLLDIG_RFMON_MUX_SEL :
bits : 1 - 4 (4 bit)
access : read-write
ADPLLDIG_RFMON_SPARE :
bits : 4 - 11 (8 bit)
access : read-write
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF_RFCU_CLK_DIV :
bits : 0 - 0 (1 bit)
access : read-write
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_EN_OVR :
bits : 0 - 1 (2 bit)
access : read-write
RX_EN_OVR :
bits : 2 - 5 (4 bit)
access : read-write
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAG_BUS0_IRQ_MASK :
bits : 0 - 0 (1 bit)
access : read-write
DIAG_BUS0_SEL :
bits : 1 - 3 (3 bit)
access : read-write
DIAG_BUS0_BIT_SEL :
bits : 3 - 8 (6 bit)
access : read-write
DIAG_BUS0_EDGE_SEL :
bits : 6 - 12 (7 bit)
access : read-write
DIAG_BUS1_IRQ_MASK :
bits : 8 - 16 (9 bit)
access : read-write
DIAG_BUS1_SEL :
bits : 9 - 19 (11 bit)
access : read-write
DIAG_BUS1_BIT_SEL :
bits : 11 - 24 (14 bit)
access : read-write
DIAG_BUS1_EDGE_SEL :
bits : 14 - 28 (15 bit)
access : read-write
DIAG_BUS2_IRQ_MASK :
bits : 16 - 32 (17 bit)
access : read-write
DIAG_BUS2_SEL :
bits : 17 - 35 (19 bit)
access : read-write
DIAG_BUS2_BIT_SEL :
bits : 19 - 40 (22 bit)
access : read-write
DIAG_BUS2_EDGE_SEL :
bits : 22 - 44 (23 bit)
access : read-write
DIAG_BUS3_IRQ_MASK :
bits : 24 - 48 (25 bit)
access : read-write
DIAG_BUS3_SEL :
bits : 25 - 51 (27 bit)
access : read-write
DIAG_BUS3_BIT_SEL :
bits : 27 - 56 (30 bit)
access : read-write
DIAG_BUS3_EDGE_SEL :
bits : 30 - 60 (31 bit)
access : read-write
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAGIRQ_STAT :
bits : 0 - 3 (4 bit)
access : read-only
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDO_RADIO_LEVEL :
bits : 0 - 2 (3 bit)
access : read-write
LDO_RADIO_CONT_ENABLE :
bits : 3 - 6 (4 bit)
access : read-write
LDO_DTC_LEVEL :
bits : 4 - 10 (7 bit)
access : read-write
LDO_DTC_CONT_ENABLE :
bits : 7 - 14 (8 bit)
access : read-write
LDO_DCO_LEVEL :
bits : 8 - 18 (11 bit)
access : read-write
LDO_DCO_CONT_ENABLE :
bits : 11 - 22 (12 bit)
access : read-write
LDO_VREF_SMPL_TIME :
bits : 16 - 36 (21 bit)
access : read-write
LDO_RADIO_HOLD_OVR_VAL :
bits : 24 - 48 (25 bit)
access : read-write
LDO_RADIO_HOLD_OVR_EN :
bits : 25 - 50 (26 bit)
access : read-write
LDO_DTC_HOLD_OVR_VAL :
bits : 26 - 52 (27 bit)
access : read-write
LDO_DTC_HOLD_OVR_EN :
bits : 27 - 54 (28 bit)
access : read-write
LDO_DCO_HOLD_OVR_VAL :
bits : 28 - 56 (29 bit)
access : read-write
LDO_DCO_HOLD_OVR_EN :
bits : 29 - 58 (30 bit)
access : read-write
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPENLOOP_RDY_SEL :
bits : 0 - 0 (1 bit)
access : read-write
OPENLOOP_RDY_WR :
bits : 1 - 2 (2 bit)
access : read-write
PWR_SW_TIM_CTRL :
bits : 4 - 10 (7 bit)
access : read-write
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