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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x190 byte (0x0)
mem_usage : registers
protection :

Registers

RF_ENABLE_CONFIG0_REG

RF_ENABLE_CONFIG4_REG

RF_CNTRL_TIMER_1_REG

RF_CNTRL_TIMER_2_REG

RF_CNTRL_TIMER_3_REG

RF_CNTRL_TIMER_4_REG

RF_CNTRL_TIMER_5_REG

RF_CNTRL_TIMER_6_REG

RF_CNTRL_TIMER_7_REG

RF_CNTRL_TIMER_8_REG

RF_CNTRL_TIMER_9_REG

RF_CNTRL_TIMER_10_REG

RF_CNTRL_TIMER_11_REG

RF_CNTRL_TIMER_12_REG

RF_CNTRL_TIMER_13_REG

RF_CNTRL_TIMER_14_REG

RF_CNTRL_TIMER_15_REG

RF_CNTRL_TIMER_16_REG

RF_ENABLE_CONFIG5_REG

RF_CNTRL_TIMER_17_REG

RF_CNTRL_TIMER_18_REG

RF_CNTRL_TIMER_19_REG

RF_CNTRL_TIMER_20_REG

RF_CNTRL_TIMER_21_REG

RF_CNTRL_TIMER_22_REG

RF_CNTRL_TIMER_23_REG

RF_CNTRL_TIMER_24_REG

RF_CNTRL_TIMER_25_REG

RF_CNTRL_TIMER_26_REG

RF_CNTRL_TIMER_27_REG

RF_CNTRL_TIMER_28_REG

RF_CNTRL_TIMER_29_REG

RF_CNTRL_TIMER_30_REG

RF_CNTRL_TIMER_31_REG

RF_ENABLE_CONFIG6_REG

RF_ALWAYS_EN1_REG

RF_ALWAYS_EN2_REG

RF_PORT_EN_REG

RF_PORT_POL_REG

RF_ENABLE_CONFIG7_REG

RF_ENABLE_CONFIG8_REG

RF_ENABLE_CONFIG9_REG

RF_ENABLE_CONFIG10_REG

RF_ENABLE_CONFIG11_REG

RF_ENABLE_CONFIG12_REG

RF_ENABLE_CONFIG13_REG

RF_ENABLE_CONFIG14_REG

RF_ENABLE_CONFIG15_REG

RF_ENABLE_CONFIG1_REG

RF_ENABLE_CONFIG16_REG

RF_ENABLE_CONFIG17_REG

RF_ENABLE_CONFIG18_REG

RF_ENABLE_CONFIG19_REG

RF_ENABLE_CONFIG20_REG

RF_ENABLE_CONFIG21_REG

RF_ENABLE_CONFIG22_REG

RF_ENABLE_CONFIG23_REG

RF_ENABLE_CONFIG24_REG

RF_ENABLE_CONFIG25_REG

RF_ENABLE_CONFIG26_REG

RF_ENABLE_CONFIG27_REG

RF_ENABLE_CONFIG28_REG

RF_ENABLE_CONFIG29_REG

RF_ENABLE_CONFIG30_REG

RF_ENABLE_CONFIG31_REG

RF_ENABLE_CONFIG2_REG

RF_ENABLE_CONFIG32_REG

RF_ENABLE_CONFIG33_REG

RF_ENABLE_CONFIG34_REG

RF_ENABLE_CONFIG35_REG

RF_ENABLE_CONFIG36_REG

RF_ENABLE_CONFIG37_REG

RF_ENABLE_CONFIG38_REG

RF_ENABLE_CONFIG39_REG

RF_ENABLE_CONFIG40_REG

RF_ENABLE_CONFIG41_REG

RF_ENABLE_CONFIG42_REG

RF_ENABLE_CONFIG43_REG

RF_ENABLE_CONFIG44_REG

RF_ENABLE_CONFIG45_REG

RF_ENABLE_CONFIG46_REG

RF_ENABLE_CONFIG3_REG


RF_ENABLE_CONFIG0_REG


address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG0_REG RF_ENABLE_CONFIG0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_LDO_EN_DCF_RX RFIO_LDO_EN_DCF_TX

RFIO_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG4_REG


address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG4_REG RF_ENABLE_CONFIG4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFF_LDO_EN_DCF_RX IFF_LDO_EN_DCF_TX

IFF_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

IFF_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_CNTRL_TIMER_1_REG


address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_1_REG RF_CNTRL_TIMER_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_2_REG


address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_2_REG RF_CNTRL_TIMER_2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_3_REG


address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_3_REG RF_CNTRL_TIMER_3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_4_REG


address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_4_REG RF_CNTRL_TIMER_4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_5_REG


address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_5_REG RF_CNTRL_TIMER_5_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_6_REG


address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_6_REG RF_CNTRL_TIMER_6_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_7_REG


address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_7_REG RF_CNTRL_TIMER_7_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_8_REG


address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_8_REG RF_CNTRL_TIMER_8_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_9_REG


address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_9_REG RF_CNTRL_TIMER_9_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_10_REG


address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_10_REG RF_CNTRL_TIMER_10_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_11_REG


address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_11_REG RF_CNTRL_TIMER_11_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_12_REG


address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_12_REG RF_CNTRL_TIMER_12_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_13_REG


address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_13_REG RF_CNTRL_TIMER_13_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_14_REG


address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_14_REG RF_CNTRL_TIMER_14_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_15_REG


address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_15_REG RF_CNTRL_TIMER_15_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_16_REG


address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_16_REG RF_CNTRL_TIMER_16_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_ENABLE_CONFIG5_REG


address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG5_REG RF_ENABLE_CONFIG5_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFFADC_LDO_EN_DCF_RX IFFADC_LDO_EN_DCF_TX

IFFADC_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

IFFADC_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_CNTRL_TIMER_17_REG


address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_17_REG RF_CNTRL_TIMER_17_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_18_REG


address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_18_REG RF_CNTRL_TIMER_18_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_19_REG


address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_19_REG RF_CNTRL_TIMER_19_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_20_REG


address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_20_REG RF_CNTRL_TIMER_20_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_21_REG


address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_21_REG RF_CNTRL_TIMER_21_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_22_REG


address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_22_REG RF_CNTRL_TIMER_22_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_23_REG


address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_23_REG RF_CNTRL_TIMER_23_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_24_REG


address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_24_REG RF_CNTRL_TIMER_24_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_25_REG


address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_25_REG RF_CNTRL_TIMER_25_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_26_REG


address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_26_REG RF_CNTRL_TIMER_26_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_27_REG


address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_27_REG RF_CNTRL_TIMER_27_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_28_REG


address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_28_REG RF_CNTRL_TIMER_28_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_29_REG


address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_29_REG RF_CNTRL_TIMER_29_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_30_REG


address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_30_REG RF_CNTRL_TIMER_30_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_CNTRL_TIMER_31_REG


address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_CNTRL_TIMER_31_REG RF_CNTRL_TIMER_31_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET_OFFSET RESET_OFFSET

SET_OFFSET :
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET :
bits : 8 - 23 (16 bit)
access : read-write


RF_ENABLE_CONFIG6_REG


address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG6_REG RF_ENABLE_CONFIG6_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_TDC_LDO_EN_DCF_RX ADPLL_TDC_LDO_EN_DCF_TX

ADPLL_TDC_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_TDC_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ALWAYS_EN1_REG


address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ALWAYS_EN1_REG RF_ALWAYS_EN1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALW_EN_RFIO_LDO_EN ALW_EN_PA_LDO_EN ALW_EN_LNA_LDO_EN ALW_EN_MIX_LDO_EN ALW_EN_IFF_LDO_EN ALW_EN_IFFADC_LDO_EN ALW_EN_ADPLL_TDC_LDO_EN ALW_EN_ADPLL_DTC_LDO_EN ALW_EN_ADPLL_DCO_LDO_EN ALW_EN_LDO_ZERO_EN ALW_EN_LNA_LDO_ZERO ALW_EN_ADPLLDIG_LDO_ACTIVERDY ALW_EN_ADPLLDIG_LDO_LP ALW_EN_RFIO_RX_EN ALW_EN_RFIO_TX_EN ALW_EN_RFIO_TX_HARM_EN ALW_EN_RFIO_BIAS_EN ALW_EN_RFIO_BIAS_SH_OPEN ALW_EN_PA_RAMP_EN ALW_EN_PA_EN ALW_EN_LNA_CORE_EN ALW_EN_LNA_CGM_EN ALW_EN_MIX_EN ALW_EN_MIX_BIAS_SH_OPEN ALW_EN_IFF_EN ALW_EN_IFF_BIAS_SH_OPEN ALW_EN_ADC_CLK_EN ALW_EN_ADC_EN ALW_EN_ADPLL_DCO_EN ALW_EN_ADPLL_CLK_EN ALW_EN_ADPLLDIG_RST ALW_EN_ADPLLDIG_EN

ALW_EN_RFIO_LDO_EN :
bits : 0 - 0 (1 bit)
access : read-write

ALW_EN_PA_LDO_EN :
bits : 1 - 2 (2 bit)
access : read-write

ALW_EN_LNA_LDO_EN :
bits : 2 - 4 (3 bit)
access : read-write

ALW_EN_MIX_LDO_EN :
bits : 3 - 6 (4 bit)
access : read-write

ALW_EN_IFF_LDO_EN :
bits : 4 - 8 (5 bit)
access : read-write

ALW_EN_IFFADC_LDO_EN :
bits : 5 - 10 (6 bit)
access : read-write

ALW_EN_ADPLL_TDC_LDO_EN :
bits : 6 - 12 (7 bit)
access : read-write

ALW_EN_ADPLL_DTC_LDO_EN :
bits : 7 - 14 (8 bit)
access : read-write

ALW_EN_ADPLL_DCO_LDO_EN :
bits : 8 - 16 (9 bit)
access : read-write

ALW_EN_LDO_ZERO_EN :
bits : 9 - 18 (10 bit)
access : read-write

ALW_EN_LNA_LDO_ZERO :
bits : 10 - 20 (11 bit)
access : read-write

ALW_EN_ADPLLDIG_LDO_ACTIVERDY :
bits : 11 - 22 (12 bit)
access : read-write

ALW_EN_ADPLLDIG_LDO_LP :
bits : 12 - 24 (13 bit)
access : read-write

ALW_EN_RFIO_RX_EN :
bits : 13 - 26 (14 bit)
access : read-write

ALW_EN_RFIO_TX_EN :
bits : 14 - 28 (15 bit)
access : read-write

ALW_EN_RFIO_TX_HARM_EN :
bits : 15 - 30 (16 bit)
access : read-write

ALW_EN_RFIO_BIAS_EN :
bits : 16 - 32 (17 bit)
access : read-write

ALW_EN_RFIO_BIAS_SH_OPEN :
bits : 17 - 34 (18 bit)
access : read-write

ALW_EN_PA_RAMP_EN :
bits : 18 - 36 (19 bit)
access : read-write

ALW_EN_PA_EN :
bits : 19 - 38 (20 bit)
access : read-write

ALW_EN_LNA_CORE_EN :
bits : 20 - 40 (21 bit)
access : read-write

ALW_EN_LNA_CGM_EN :
bits : 21 - 42 (22 bit)
access : read-write

ALW_EN_MIX_EN :
bits : 22 - 44 (23 bit)
access : read-write

ALW_EN_MIX_BIAS_SH_OPEN :
bits : 23 - 46 (24 bit)
access : read-write

ALW_EN_IFF_EN :
bits : 24 - 48 (25 bit)
access : read-write

ALW_EN_IFF_BIAS_SH_OPEN :
bits : 25 - 50 (26 bit)
access : read-write

ALW_EN_ADC_CLK_EN :
bits : 26 - 52 (27 bit)
access : read-write

ALW_EN_ADC_EN :
bits : 27 - 54 (28 bit)
access : read-write

ALW_EN_ADPLL_DCO_EN :
bits : 28 - 56 (29 bit)
access : read-write

ALW_EN_ADPLL_CLK_EN :
bits : 29 - 58 (30 bit)
access : read-write

ALW_EN_ADPLLDIG_RST :
bits : 30 - 60 (31 bit)
access : read-write

ALW_EN_ADPLLDIG_EN :
bits : 31 - 62 (32 bit)
access : read-write


RF_ALWAYS_EN2_REG


address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ALWAYS_EN2_REG RF_ALWAYS_EN2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALW_EN_ADPLLDIG_RX_EN ALW_EN_ADPLL_PAIN_EN ALW_EN_ADPLL_LOBUF_PA_EN ALW_EN_CAL_EN ALW_EN_DEM_EN ALW_EN_DEM_DC_PARCAL_EN ALW_EN_DEM_AGC_UNFREEZE_EN ALW_EN_DEM_SIGDETECT_EN ALW_EN_PHY_RDY4BS ALW_EN_ADPLL_RDY_FOR_DIV ALW_EN_SPARE1 ALW_EN_SPARE2 ALW_EN_SPARE3 ALW_EN_SPARE4 ALW_EN_SPARE5

ALW_EN_ADPLLDIG_RX_EN :
bits : 0 - 0 (1 bit)
access : read-write

ALW_EN_ADPLL_PAIN_EN :
bits : 1 - 2 (2 bit)
access : read-write

ALW_EN_ADPLL_LOBUF_PA_EN :
bits : 2 - 4 (3 bit)
access : read-write

ALW_EN_CAL_EN :
bits : 3 - 6 (4 bit)
access : read-write

ALW_EN_DEM_EN :
bits : 4 - 8 (5 bit)
access : read-write

ALW_EN_DEM_DC_PARCAL_EN :
bits : 5 - 10 (6 bit)
access : read-write

ALW_EN_DEM_AGC_UNFREEZE_EN :
bits : 6 - 12 (7 bit)
access : read-write

ALW_EN_DEM_SIGDETECT_EN :
bits : 7 - 14 (8 bit)
access : read-write

ALW_EN_PHY_RDY4BS :
bits : 8 - 16 (9 bit)
access : read-write

ALW_EN_ADPLL_RDY_FOR_DIV :
bits : 9 - 18 (10 bit)
access : read-write

ALW_EN_SPARE1 :
bits : 10 - 20 (11 bit)
access : read-write

ALW_EN_SPARE2 :
bits : 11 - 22 (12 bit)
access : read-write

ALW_EN_SPARE3 :
bits : 12 - 24 (13 bit)
access : read-write

ALW_EN_SPARE4 :
bits : 13 - 26 (14 bit)
access : read-write

ALW_EN_SPARE5 :
bits : 14 - 28 (15 bit)
access : read-write


RF_PORT_EN_REG


address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_PORT_EN_REG RF_PORT_EN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_PORT0_RX RF_PORT0_TX RF_PORT1_RX RF_PORT1_TX RF_PORT2_RX RF_PORT2_TX RF_PORT3_RX RF_PORT3_TX RF_PORT4_RX RF_PORT4_TX

RF_PORT0_RX :
bits : 0 - 0 (1 bit)
access : read-write

RF_PORT0_TX :
bits : 1 - 2 (2 bit)
access : read-write

RF_PORT1_RX :
bits : 2 - 4 (3 bit)
access : read-write

RF_PORT1_TX :
bits : 3 - 6 (4 bit)
access : read-write

RF_PORT2_RX :
bits : 4 - 8 (5 bit)
access : read-write

RF_PORT2_TX :
bits : 5 - 10 (6 bit)
access : read-write

RF_PORT3_RX :
bits : 6 - 12 (7 bit)
access : read-write

RF_PORT3_TX :
bits : 7 - 14 (8 bit)
access : read-write

RF_PORT4_RX :
bits : 8 - 16 (9 bit)
access : read-write

RF_PORT4_TX :
bits : 9 - 18 (10 bit)
access : read-write


RF_PORT_POL_REG


address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_PORT_POL_REG RF_PORT_POL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_PORT0_POL RF_PORT1_POL RF_PORT2_POL RF_PORT3_POL RF_PORT4_POL

RF_PORT0_POL :
bits : 0 - 0 (1 bit)
access : read-write

RF_PORT1_POL :
bits : 1 - 2 (2 bit)
access : read-write

RF_PORT2_POL :
bits : 2 - 4 (3 bit)
access : read-write

RF_PORT3_POL :
bits : 3 - 6 (4 bit)
access : read-write

RF_PORT4_POL :
bits : 4 - 8 (5 bit)
access : read-write


RF_ENABLE_CONFIG7_REG


address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG7_REG RF_ENABLE_CONFIG7_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_DTC_LDO_EN_DCF_RX ADPLL_DTC_LDO_EN_DCF_TX

ADPLL_DTC_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_DTC_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG8_REG


address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG8_REG RF_ENABLE_CONFIG8_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_DCO_LDO_EN_DCF_RX ADPLL_DCO_LDO_EN_DCF_TX

ADPLL_DCO_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_DCO_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG9_REG


address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG9_REG RF_ENABLE_CONFIG9_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO_ZERO_EN_DCF_RX LDO_ZERO_EN_DCF_TX

LDO_ZERO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

LDO_ZERO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG10_REG


address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG10_REG RF_ENABLE_CONFIG10_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNA_LDO_ZERO_DCF_RX LNA_LDO_ZERO_DCF_TX

LNA_LDO_ZERO_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

LNA_LDO_ZERO_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG11_REG


address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG11_REG RF_ENABLE_CONFIG11_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_LDO_ACTIVERDY_DCF_RX ADPLLDIG_LDO_ACTIVERDY_DCF_TX

ADPLLDIG_LDO_ACTIVERDY_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_LDO_ACTIVERDY_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG12_REG


address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG12_REG RF_ENABLE_CONFIG12_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_LDO_LP_DCF_RX ADPLLDIG_LDO_LP_DCF_TX

ADPLLDIG_LDO_LP_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_LDO_LP_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG13_REG


address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG13_REG RF_ENABLE_CONFIG13_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_RX_EN_DCF_RX RFIO_RX_EN_DCF_TX

RFIO_RX_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_RX_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG14_REG


address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG14_REG RF_ENABLE_CONFIG14_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_TX_EN_DCF_RX RFIO_TX_EN_DCF_TX

RFIO_TX_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_TX_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG15_REG


address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG15_REG RF_ENABLE_CONFIG15_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_TX_HARM_EN_DCF_RX RFIO_TX_HARM_EN_DCF_TX

RFIO_TX_HARM_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_TX_HARM_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG1_REG


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG1_REG RF_ENABLE_CONFIG1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_LDO_EN_DCF_RX PA_LDO_EN_DCF_TX

PA_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

PA_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG16_REG


address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG16_REG RF_ENABLE_CONFIG16_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_BIAS_EN_DCF_RX RFIO_BIAS_EN_DCF_TX

RFIO_BIAS_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_BIAS_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG17_REG


address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG17_REG RF_ENABLE_CONFIG17_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFIO_BIAS_SH_OPEN_DCF_RX RFIO_BIAS_SH_OPEN_DCF_TX

RFIO_BIAS_SH_OPEN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

RFIO_BIAS_SH_OPEN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG18_REG


address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG18_REG RF_ENABLE_CONFIG18_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_RAMP_EN_DCF_RX PA_RAMP_EN_DCF_TX

PA_RAMP_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

PA_RAMP_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG19_REG


address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG19_REG RF_ENABLE_CONFIG19_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_EN_DCF_RX PA_EN_DCF_TX

PA_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

PA_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG20_REG


address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG20_REG RF_ENABLE_CONFIG20_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNA_CORE_EN_DCF_RX LNA_CORE_EN_DCF_TX

LNA_CORE_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

LNA_CORE_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG21_REG


address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG21_REG RF_ENABLE_CONFIG21_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNA_CGM_EN_DCF_RX LNA_CGM_EN_DCF_TX

LNA_CGM_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

LNA_CGM_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG22_REG


address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG22_REG RF_ENABLE_CONFIG22_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIX_EN_DCF_RX MIX_EN_DCF_TX

MIX_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

MIX_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG23_REG


address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG23_REG RF_ENABLE_CONFIG23_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIX_BIAS_SH_OPEN_DCF_RX MIX_BIAS_SH_OPEN_DCF_TX

MIX_BIAS_SH_OPEN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

MIX_BIAS_SH_OPEN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG24_REG


address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG24_REG RF_ENABLE_CONFIG24_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFF_EN_DCF_RX IFF_EN_DCF_TX

IFF_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

IFF_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG25_REG


address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG25_REG RF_ENABLE_CONFIG25_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFF_BIAS_SH_OPEN_DCF_RX IFF_BIAS_SH_OPEN_DCF_TX

IFF_BIAS_SH_OPEN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

IFF_BIAS_SH_OPEN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG26_REG


address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG26_REG RF_ENABLE_CONFIG26_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CLK_EN_DCF_RX ADC_CLK_EN_DCF_TX

ADC_CLK_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADC_CLK_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG27_REG


address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG27_REG RF_ENABLE_CONFIG27_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_EN_DCF_RX ADC_EN_DCF_TX

ADC_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADC_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG28_REG


address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG28_REG RF_ENABLE_CONFIG28_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_DCO_EN_DCF_RX ADPLL_DCO_EN_DCF_TX

ADPLL_DCO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_DCO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG29_REG


address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG29_REG RF_ENABLE_CONFIG29_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_CLK_EN_DCF_RX ADPLL_CLK_EN_DCF_TX

ADPLL_CLK_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_CLK_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG30_REG


address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG30_REG RF_ENABLE_CONFIG30_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_RST_DCF_RX ADPLLDIG_RST_DCF_TX

ADPLLDIG_RST_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_RST_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG31_REG


address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG31_REG RF_ENABLE_CONFIG31_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_EN_DCF_RX ADPLLDIG_EN_DCF_TX

ADPLLDIG_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG2_REG


address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG2_REG RF_ENABLE_CONFIG2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNA_LDO_EN_DCF_RX LNA_LDO_EN_DCF_TX

LNA_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

LNA_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG32_REG


address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG32_REG RF_ENABLE_CONFIG32_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_RX_EN_DCF_RX ADPLLDIG_RX_EN_DCF_TX

ADPLLDIG_RX_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_RX_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG33_REG


address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG33_REG RF_ENABLE_CONFIG33_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLLDIG_PAIN_EN_DCF_RX ADPLLDIG_PAIN_EN_DCF_TX

ADPLLDIG_PAIN_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLLDIG_PAIN_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG34_REG


address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG34_REG RF_ENABLE_CONFIG34_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_LOBUF_PA_EN_DCF_RX ADPLL_LOBUF_PA_EN_DCF_TX

ADPLL_LOBUF_PA_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_LOBUF_PA_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG35_REG


address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG35_REG RF_ENABLE_CONFIG35_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL_EN_DCF_RX CAL_EN_DCF_TX

CAL_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

CAL_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG36_REG


address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG36_REG RF_ENABLE_CONFIG36_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEM_EN_DCF_RX DEM_EN_DCF_TX

DEM_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

DEM_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG37_REG


address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG37_REG RF_ENABLE_CONFIG37_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEM_DC_PARCAL_EN_DCF_RX SPARE_DEM_DC_PARCAL_DCF_TX

DEM_DC_PARCAL_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE_DEM_DC_PARCAL_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG38_REG


address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG38_REG RF_ENABLE_CONFIG38_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEM_AGC_UNFREEZE_EN_DCF_RX SPARE_DEM_AGC_UNFREEZE_EN_DCF_TX

DEM_AGC_UNFREEZE_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE_DEM_AGC_UNFREEZE_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG39_REG


address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG39_REG RF_ENABLE_CONFIG39_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEM_SIGDETECT_EN_DCF_RX SPARE_DEM_SIGDETECT_EN_DCF_TX

DEM_SIGDETECT_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE_DEM_SIGDETECT_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG40_REG


address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG40_REG RF_ENABLE_CONFIG40_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_RDY4BS_DCF_RX PHY_RDY4BS_DCF_TX

PHY_RDY4BS_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

PHY_RDY4BS_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG41_REG


address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG41_REG RF_ENABLE_CONFIG41_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADPLL_RDY_FOR_DIV_DCF_RX ADPLL_RDY_FOR_DIV_DCF_TX

ADPLL_RDY_FOR_DIV_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

ADPLL_RDY_FOR_DIV_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG42_REG


address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG42_REG RF_ENABLE_CONFIG42_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE1_DCF_RX SPARE1_DCF_TX

SPARE1_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE1_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG43_REG


address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG43_REG RF_ENABLE_CONFIG43_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE2_DCF_RX SPARE2_DCF_TX

SPARE2_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE2_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG44_REG


address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG44_REG RF_ENABLE_CONFIG44_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE3_DCF_RX SPARE3_DCF_TX

SPARE3_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE3_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG45_REG


address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG45_REG RF_ENABLE_CONFIG45_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE4_DCF_RX SPARE4_DCF_TX

SPARE4_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE4_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG46_REG


address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG46_REG RF_ENABLE_CONFIG46_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE5_DCF_RX SPARE5_DCF_TX

SPARE5_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

SPARE5_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write


RF_ENABLE_CONFIG3_REG


address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_ENABLE_CONFIG3_REG RF_ENABLE_CONFIG3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIX_LDO_EN_DCF_RX MIX_LDO_EN_DCF_TX

MIX_LDO_EN_DCF_RX :
bits : 0 - 4 (5 bit)
access : read-write

MIX_LDO_EN_DCF_TX :
bits : 5 - 14 (10 bit)
access : read-write



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