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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL_REG

CRV_ADDR_REG

CRV_LEN_REG

ADDR_REG

LEN_REG

STAT_REG


CTRL_REG

Control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_REG CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_PACK_EN RFMON_CIRC_EN

RFMON_PACK_EN : Starts the capturing of the data from the test bus 0 : There is no capturing of data. 1 : The controller captures data. Should be written with 1 in order to start the acquisition of data. If the controller is not in circular mode (RFMON_CIRC_EN = 0) and after capturing a predefined number of words (RFMON_LEN), this bit will be auto cleared. In circular mode (RFMON_CIRC_EN = 1) the RFMON_PACK_EN remains 1 until to be cleared by the software.
bits : 0 - 0 (1 bit)
access : read-write

RFMON_CIRC_EN : Write with 1 to enable the circular mode.In circular mode the controller continuously writes data in to the memory until to be disabled by the software. The data are transferred in the circular buffer in the memory, which is defined by the RFMON_ADDR_REG and the RFMON_LEN_REG registers. The disabling of the controller is realized by writing the RFMON_PACK_EN with 0.
bits : 1 - 2 (2 bit)
access : read-write


CRV_ADDR_REG

AHB master current address
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRV_ADDR_REG CRV_ADDR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_CRV_ADDR

RFMON_CRV_ADDR : It is the bits [15:2] of AHB address that will be used by the controller in the next memory access. The bits [1:0] are always 0.
bits : 2 - 17 (16 bit)
access : read-only


CRV_LEN_REG

The remaining data to be transferred
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRV_LEN_REG CRV_LEN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_CRV_LEN

RFMON_CRV_LEN : Indicates the number of words (minus 1) that remain to be transfered.
bits : 0 - 13 (14 bit)
access : read-only


ADDR_REG

AHB master start address
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_REG ADDR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_ADDR

RFMON_ADDR : It is the bits [15:2] of base address that is used by the AHB master interface of the controller. Defines the AHB address from where the controller will start to stores data. The bits [1:0] of the address are considered always 0.
bits : 2 - 17 (16 bit)
access : read-write


LEN_REG

Data length register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEN_REG LEN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_LEN

RFMON_LEN : The number of words (minus one) that should be captured.
bits : 0 - 13 (14 bit)
access : read-write


STAT_REG

Status register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT_REG STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFMON_ACTIVE RFMON_OFLOW_STK

RFMON_ACTIVE : Indicates the state of the controller. 0 : The controller is idle. 1 : The controller is active. The capturing process and/or the dma activity is in progress. The controller will be activated (RFMON_ACTIVE == 1), when RFMON_PACK_EN will be written with 1. Will return to inactive state, after the end of the capturing process (RFMON_PACK_EN==0) and the completion of the transfer of all of the data to the memory.
bits : 0 - 0 (1 bit)
access : read-only

RFMON_OFLOW_STK : Indicates that during the transfer of the data, at least one overflow has detected to the fifo. 0 : The transfer completed without overflows. 1 : At least one overflow occured in the fifo. Write 1 to clear this bit.
bits : 1 - 2 (2 bit)
access : read-write



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