CTRL_REG

IRQ_MASK_REG

STATUS_REG

FIFO_STATUS_REG

FIFO_READ_REG

FIFO_WRITE_REG

CS_CONFIG_REG

FIFO_HIGH_REG

TXBUFFER_FORCE_L_REG

TXBUFFER_FORCE_H_REG

CONFIG_REG

CLOCK_REG

FIFO_CONFIG_REG

SPI_EN : 0 = SPI module is disable 1 = SPI module is enable
bits : 0 - 0 (1 bit)
access : read-write

SPI_TX_EN : 0 = TX path is disabled 1 = TX path is enabled
bits : 1 - 2 (2 bit)
access : read-write

SPI_RX_EN : 0 = RX path is disabled 1 = RX path is enabled Note: if master clk async or spi mode=1 or spi mode=3 readonly is not supported
bits : 2 - 4 (3 bit)
access : read-write

SPI_DMA_TX_EN : applicable only when SPI_TX_EN=1 0 = No DMA request for TX 1 = DMA request when SPI_STATUS_TX_EMPTY='1'
bits : 3 - 6 (4 bit)
access : read-write

SPI_DMA_RX_EN : applicable only when SPI_RX_EN=1 0 = No DMA request for RX 1 = DMA request when SPI_STATUS_RX_FULL='1'
bits : 4 - 8 (5 bit)
access : read-write

SPI_FIFO_RESET : 0 = Fifo normal operation 1 = Fifo in reset state
bits : 5 - 10 (6 bit)
access : read-write

SPI_CAPTURE_AT_NEXT_EDGE : 0 = SPI captures data at correct clock edge 1 = SPI captures data at next clock edge. (only for Master mode and high clock)
bits : 6 - 12 (7 bit)
access : read-write

SPI_SWAP_BYTES : 0 = normal operation 1 = LSB and MSB are swaped in APB interface In case of 8bit spi interface, DMA/SPI can be configured in 16bit mode to off load the bus. Enabling SPI_SWAP_BYTES bytes will read/wrte correctly
bits : 7 - 14 (8 bit)
access : read-write

SPI_IRQ_MASK_TX_EMPTY : 0 = FIFO TX empty irq is masked 1 = FIFO TX empy irq is enabled
bits : 0 - 0 (1 bit)
access : read-write

SPI_IRQ_MASK_RX_FULL : 0 = FIFO RX full irq is masked 1 = FIFO RX full irq is enabled
bits : 1 - 2 (2 bit)
access : read-write

SPI_STATUS_TX_EMPTY : Auto clear 0 = TX fifo level is larger than SPI_TX_TL 1 = TX fifo level is less or equal to SPI_TX_TL
bits : 0 - 0 (1 bit)
access : read-only

SPI_STATUS_RX_FULL : Auto clear 0 = RX fifo level is less than SPI_RX_TL+1 1 = RX fifo level is more or equal to SPI_RX_TL+1
bits : 1 - 2 (2 bit)
access : read-only

SPI_RX_FIFO_LEVEL : Gives the number of bytes in RX fifo
bits : 0 - 5 (6 bit)
access : read-only

SPI_TX_FIFO_LEVEL : Gives the number of bytes in TX fifo
bits : 6 - 17 (12 bit)
access : read-only

SPI_STATUS_RX_EMPTY : 0 = RX fifo is not empty 1 = RX fifo is empty
bits : 12 - 24 (13 bit)
access : read-only

SPI_STATUS_TX_FULL : 0 = TX fifo is not full 1 = TX fifo is full
bits : 13 - 26 (14 bit)
access : read-only

SPI_RX_FIFO_OVFL : When 1, receive data is not written to fifo because fifo was full and interrupt is generated. It clears with SPI_CTRL_REG.SPI_FIFO_RESET
bits : 14 - 28 (15 bit)
access : read-only

SPI_TRANSACTION_ACTIVE : In master mode 0 = spi transaction is inactive 1 = spi transaction is active
bits : 15 - 30 (16 bit)
access : read-only

SPI_FIFO_READ : Read from RX fifo. Read access is permit only if SPI_RX_FIFO_EMPTY=0. Returns the 16 LSb
bits : 0 - 15 (16 bit)
access : read-only

SPI_FIFO_WRITE : Write to TX fifo. Write access is permit only if SPI_TX_FIFO_FULL is 0
bits : 0 - 15 (16 bit)
access : write-only

SPI_CS_SELECT : Control the cs output in master mode 0 = none slave device selected 1 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS0 2 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS1 4 = selected slave device connected to GPIO with FUNC_MODE=GPIO
bits : 0 - 2 (3 bit)
access : read-write

SPI_FIFO_HIGH : RX/TX fifo data. 16 MSb when spi word is larger than 16bits This register has to be written before the SPI_FIFO_WRITE_REG This register has to be read after the SPI_FIFO_READ_REG
bits : 0 - 15 (16 bit)
access : read-write

SPI_TXBUFFER_FORCE_L : Write directly the tx buffer (2 LSB). It must to be used only in slave mode
bits : 0 - 15 (16 bit)
access : write-only

SPI_TXBUFFER_FORCE_H : Write directly the tx buffer (2 MSB). It must to be used only in slave mode. This register has to be written before the SPI_FIFO_WRITE_REG
bits : 0 - 15 (16 bit)
access : write-only

SPI_MODE : Define the spi mode (CPOL, CPHA) 0 = new data on falling, capture on rising, clk low in idle state 1 = new data on rising, capture on falling, Clk low in idle state 2 = new data on rising, capture on falling, Clk high in idle state 3 = new data on falling, capture on rising Clk high in idle state
bits : 0 - 1 (2 bit)
access : read-write

SPI_WORD_LENGTH : Define the spi word length = 1+ SPI_WORD_LENGTH (range 4 to 32)
bits : 2 - 8 (7 bit)
access : read-write

SPI_SLAVE_EN : 0 = SPI module master mode 1 = SPI module slave mode
bits : 7 - 14 (8 bit)
access : read-write

SPI_CLK_DIV : Applicable only in master mode Defines the spi clock frequency in master only mode SPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) when SPI_CLK_DIV not 0x7F if SPI_CLK_DIV=0x7F then SPI_CLK=module_clk
bits : 0 - 6 (7 bit)
access : read-write

SPI_MASTER_CLK_MODE : Should be always 1
bits : 7 - 14 (8 bit)
access : read-write

SPI_TX_TL : Transmit FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the TX_EMPTY interrupt. IRQ is occurred when fifo level is less or equal to SPI_TX_TL. Fifo level is from 0 to 4
bits : 0 - 3 (4 bit)
access : read-write

SPI_RX_TL : Receive FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the RX_FULL interrupt. IRQ is occurred when fifo level is more or equal to SPI_RX_TL+1. Fifo level is from 0 to 4
bits : 4 - 11 (8 bit)
access : read-write