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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL_REG

PWM5_START_CYCLE

PWM6_START_CYCLE

PWM7_START_CYCLE

PWM2_END_CYCLE

PWM3_END_CYCLE

PWM4_END_CYCLE

PWM5_END_CYCLE

PWM6_END_CYCLE

ON_REG

PWM7_END_CYCLE

TRIPLE_PWM_CTRL_REG

RELOAD_M_REG

RELOAD_N_REG

TRIPLE_PWM_FREQUENCY

PWM2_START_CYCLE

PWM3_START_CYCLE

PWM4_START_CYCLE


CTRL_REG

Timer0 control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_REG CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_CTRL TIM0_CLK_SEL TIM0_CLK_DIV PWM_MODE

TIM0_CTRL : 0 = Timer0 is off and in reset state. 1 = Timer0 is running.
bits : 0 - 0 (1 bit)
access : read-write

TIM0_CLK_SEL : 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses LP clock
bits : 1 - 2 (2 bit)
access : read-write

TIM0_CLK_DIV : 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter.
bits : 2 - 4 (3 bit)
access : read-write

PWM_MODE : 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz.
bits : 3 - 6 (4 bit)
access : read-write


PWM5_START_CYCLE

Defines start Cycle for PWM5
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM5_START_CYCLE PWM5_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM6_START_CYCLE

Defines start Cycle for PWM6
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM6_START_CYCLE PWM6_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM7_START_CYCLE

Defines start Cycle for PWM7
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM7_START_CYCLE PWM7_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM2_END_CYCLE

Defines end Cycle for PWM2
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2_END_CYCLE PWM2_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


PWM3_END_CYCLE

Defines end Cycle for PWM3
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3_END_CYCLE PWM3_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


PWM4_END_CYCLE

Defines end Cycle for PWM4
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM4_END_CYCLE PWM4_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


PWM5_END_CYCLE

Defines end Cycle for PWM5
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM5_END_CYCLE PWM5_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


PWM6_END_CYCLE

Defines end Cycle for PWM6
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM6_END_CYCLE PWM6_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


ON_REG

Timer0 on control register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ON_REG ON_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_ON

TIM0_ON : Timer0 On reload value: If read the actual counter value ON_CNTer is returned
bits : 0 - 15 (16 bit)
access : read-write


PWM7_END_CYCLE

Defines end Cycle for PWM7
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM7_END_CYCLE PWM7_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


TRIPLE_PWM_CTRL_REG

PWM 2,3,4,5,6,7 Control
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_CTRL_REG TRIPLE_PWM_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIPLE_PWM_ENABLE SW_PAUSE_EN HW_PAUSE_EN TRIPLE_PWM_CLK_SEL

TRIPLE_PWM_ENABLE : '1' = enable PWM 2 3 4 5 6 7
bits : 0 - 0 (1 bit)
access : read-write

SW_PAUSE_EN : '1' = PWM 2 3 4 5 6 7 are paused
bits : 1 - 2 (2 bit)
access : read-write

HW_PAUSE_EN : '1' = HW can pause PWM 2,3,4,5,6,7
bits : 2 - 4 (3 bit)
access : read-write

TRIPLE_PWM_CLK_SEL : 1 = Timer2 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer2 uses LP clock
bits : 3 - 6 (4 bit)
access : read-write


RELOAD_M_REG

16 bits reload value for Timer0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELOAD_M_REG RELOAD_M_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_M

TIM0_M : Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : read-write


RELOAD_N_REG

16 bits reload value for Timer0
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RELOAD_N_REG RELOAD_N_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_N

TIM0_N : Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : read-write


TRIPLE_PWM_FREQUENCY

Frequency for PWM 2,3,4,5,6 and 7
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_FREQUENCY TRIPLE_PWM_FREQUENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM_FREQ

PWM_FREQ : Defines the frequeancy of PWM 2,3,4,5,,6 and 7. pwm freq = module Frequency / (value+1) module frequency is the LP_CLK when TRIPLE_PWM_CLK_SEL=0 else is the sys_clk divided by TMR_DIV
bits : 0 - 13 (14 bit)
access : read-write


PWM2_START_CYCLE

Defines start Cycle for PWM2
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2_START_CYCLE PWM2_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM3_START_CYCLE

Defines start Cycle for PWM3
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3_START_CYCLE PWM3_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM4_START_CYCLE

Defines start Cycle for PWM4
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM4_START_CYCLE PWM4_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write



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