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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL_REG

CAPCNT2_VALUE_REG

CLR_EVENT_REG

CAPTURE_REG

STATUS_REG

CAPCNT1_VALUE_REG


CTRL_REG

Timer1 control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_REG CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_RELOAD TIMER1_ENABLE TIMER1_COUNT_DOWN_EN TIMER1_IRQ_EN TIMER1_FREE_RUN_MODE_EN TIMER1_USE_SYS_CLK TIMER1_CLK_EN

TIMER1_RELOAD : Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles)
bits : 0 - 10 (11 bit)
access : read-write

TIMER1_ENABLE : 0 = Timer1 disabled 1 = Timer1 enabled
bits : 11 - 22 (12 bit)
access : read-write

TIMER1_COUNT_DOWN_EN : 0 = timer1 counts up 1 = timer1 counts down
bits : 12 - 24 (13 bit)
access : read-write

TIMER1_IRQ_EN : 0 = timer1 IRQ masked 1 = timer1 IRQ unmasked
bits : 13 - 26 (14 bit)
access : read-write

TIMER1_FREE_RUN_MODE_EN : Applicable when timer counts up 1 = timer1 goes to zero when it reaches the max value. 0 = timer1 goes to zero when it reaches the reload value.
bits : 14 - 28 (15 bit)
access : read-write

TIMER1_USE_SYS_CLK : 0 = Timer1 use the clock LP clock 1 = Timer1 use the system clock
bits : 15 - 30 (16 bit)
access : read-write

TIMER1_CLK_EN : 0 = timer1 clock is disabled 1 = timer1 clock is enabled
bits : 16 - 32 (17 bit)
access : read-write


CAPCNT2_VALUE_REG

Timer1 value for event on GPIO2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCNT2_VALUE_REG CAPCNT2_VALUE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_CAPCNT2_VALUE TIMER1_CAPCNT2_RTC_HIGH

TIMER1_CAPCNT2_VALUE : In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN2_PERIOD_MAX periods of IN2 In Capture mode (TIMER1_IN2_STAMP_TYPE=0) : Gives the Counter value when an IN2 event was occurred In Capture mode (TIMER1_IN2_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN2 event was occurred
bits : 0 - 10 (11 bit)
access : read-only

TIMER1_CAPCNT2_RTC_HIGH : In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN2 event was occurred
bits : 11 - 32 (22 bit)
access : read-only


CLR_EVENT_REG

Clear event register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLR_EVENT_REG CLR_EVENT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_CLR_TIMER_EVENT TIMER1_CLR_IN1_EVENT TIMER1_CLR_IN2_EVENT

TIMER1_CLR_TIMER_EVENT : Write 1 to clear the TIMER1_TIMER_EVENT
bits : 0 - 0 (1 bit)
access : read-write

TIMER1_CLR_IN1_EVENT : Write 1 to clear the TIMER1_IN1_EVENT and TIMER1_IN1_OVRFLW
bits : 1 - 2 (2 bit)
access : read-write

TIMER1_CLR_IN2_EVENT : Write 1 to clear the TIMER1_IN2_EVENT and TIMER1_IN2_OVRFLW
bits : 2 - 4 (3 bit)
access : read-write


CAPTURE_REG

Timer1 Capture control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPTURE_REG CAPTURE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_GPIO1_CONF TIMER1_IN1_EVENT_FALL_EN TIMER1_IN1_COUNT_EN TIMER1_IN1_IRQ_EN TIMER1_IN1_PERIOD_MAX TIMER1_IN1_STAMP_TYPE TIMER1_GPIO2_CONF TIMER1_IN2_EVENT_FALL_EN TIMER1_IN2_COUNT_EN TIMER1_IN2_IRQ_EN TIMER1_IN2_PERIOD_MAX TIMER1_IN2_STAMP_TYPE

TIMER1_GPIO1_CONF : 0,13,14,15 = IN1 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN1
bits : 0 - 3 (4 bit)
access : read-write

TIMER1_IN1_EVENT_FALL_EN : 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO1_CONF=0 to prevent false events
bits : 4 - 8 (5 bit)
access : read-write

TIMER1_IN1_COUNT_EN : 0 = Capture mode 1 = Count mode
bits : 5 - 10 (6 bit)
access : read-write

TIMER1_IN1_IRQ_EN : 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN1_PERIOD_MAX 0 = Interrupt is masked
bits : 6 - 12 (7 bit)
access : read-write

TIMER1_IN1_PERIOD_MAX : Gives the number of periods +1 of IN1, in which module counts
bits : 7 - 19 (13 bit)
access : read-write

TIMER1_IN1_STAMP_TYPE : 0 = On each event store the counter value 1 = On each event store the RTC time stamp
bits : 13 - 26 (14 bit)
access : read-write

TIMER1_GPIO2_CONF : 0,13,14,15 = IN2 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN2
bits : 14 - 31 (18 bit)
access : read-write

TIMER1_IN2_EVENT_FALL_EN : 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO2_CONF=0 to prevent false events
bits : 18 - 36 (19 bit)
access : read-write

TIMER1_IN2_COUNT_EN : 0 = Capture mode 1 = Count mode
bits : 19 - 38 (20 bit)
access : read-write

TIMER1_IN2_IRQ_EN : 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN2_PERIOD_MAX 0 = Interrupt is masked
bits : 20 - 40 (21 bit)
access : read-write

TIMER1_IN2_PERIOD_MAX : Gives the number of periods +1 of IN2, in which module counts
bits : 21 - 47 (27 bit)
access : read-write

TIMER1_IN2_STAMP_TYPE : 0 = On each event store the counter value 1 = On each event store the RTC time stamp
bits : 27 - 54 (28 bit)
access : read-write


STATUS_REG

Timer1 counter value
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_REG STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_TIMER_VALUE TIMER1_TIMER_EVENT TIMER1_IN1_EVENT TIMER1_IN2_EVENT TIMER1_IN1_OVRFLW TIMER1_IN2_OVRFLW

TIMER1_TIMER_VALUE : Gives the current timer value
bits : 0 - 10 (11 bit)
access : read-only

TIMER1_TIMER_EVENT : 1 = Pending Timer interrupt. it has be clear writing 1' to TIMER1_CLR_TIMER_EVENT
bits : 11 - 22 (12 bit)
access : read-only

TIMER1_IN1_EVENT : 1 = Pending Capture 1 interrupt. It has be clear writing 1 to TIMER1_CLR_IN1_EVENT
bits : 12 - 24 (13 bit)
access : read-only

TIMER1_IN2_EVENT : 1 = Pending Capture 2 interrupt. It has be clear writing 1 to TIMER1_CLR_IN2_EVENT
bits : 13 - 26 (14 bit)
access : read-only

TIMER1_IN1_OVRFLW : 1 = New IN1 event occurred while Interrupt was pending. TIMER1_CAPCNT1_VALUE_REG gives the time stamp of the first event.
bits : 14 - 28 (15 bit)
access : read-only

TIMER1_IN2_OVRFLW : 1 = New IN2 event occurred while Interrupt was pending. TIMER1_CAPCNT2_VALUE_REG gives the time stamp of the first event.
bits : 15 - 30 (16 bit)
access : read-only


CAPCNT1_VALUE_REG

Timer1 value for event on GPIO1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCNT1_VALUE_REG CAPCNT1_VALUE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_CAPCNT1_VALUE TIMER1_CAPCNT1_RTC_HIGH

TIMER1_CAPCNT1_VALUE : In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN1_PERIOD_MAX periods of IN1 In Capture mode (TIMER1_IN1_STAMP_TYPE=0) : Gives the Counter value when an IN1 event was occurred In Capture mode (TIMER1_IN1_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN1 event was occurred
bits : 0 - 10 (11 bit)
access : read-only

TIMER1_CAPCNT1_RTC_HIGH : In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN1 event was occurred
bits : 11 - 32 (22 bit)
access : read-only



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