BLE_RWBTLECNTL_REG

BLE_INTSTAT_REG

BLE_INTRAWSTAT_REG

BLE_INTACK_REG

BLE_BASETIMECNT_REG

BLE_FINETIMECNT_REG

BLE_CNTL2_REG

BLE_RF_DIAGIRQ_REG

BLE_BDADDRL_REG

BLE_BDADDRU_REG

BLE_CURRENTRXDESCPTR_REG

BLE_DEEPSLCNTL_REG

BLE_DEEPSLWKUP_REG

BLE_DEEPSLSTAT_REG

BLE_ENBPRESET_REG

BLE_VERSION_REG

BLE_FINECNTCORR_REG

BLE_BASETIMECNTCORR_REG

BLE_DIAGCNTL_REG

BLE_DIAGSTAT_REG

BLE_DEBUGADDMAX_REG

BLE_DEBUGADDMIN_REG

BLE_ERRORTYPESTAT_REG

BLE_SWPROFILING_REG

BLE_RADIOCNTL0_REG

BLE_RADIOCNTL1_REG

BLE_RWBTLECONF_REG

BLE_RADIOPWRUPDN_REG

BLE_ADVCHMAP_REG

BLE_ADVTIM_REG

BLE_ACTSCANSTAT_REG

BLE_WLPUBADDPTR_REG

BLE_WLPRIVADDPTR_REG

BLE_WLNBDEV_REG

BLE_INTCNTL_REG

BLE_AESCNTL_REG

BLE_AESKEY31_0_REG

BLE_AESKEY63_32_REG

BLE_AESKEY95_64_REG

BLE_AESKEY127_96_REG

BLE_AESPTR_REG

BLE_TXMICVAL_REG

BLE_RXMICVAL_REG

BLE_RFTESTCNTL_REG

BLE_TIMGENCNTL_REG

BLE_GROSSTIMTGT_REG

BLE_FINETIMTGT_REG

BLE_SAMPLECLK_REG

SYNCERR : Indicates the maximum number of errors allowed to recognize the synchronization word.
bits : 0 - 2 (3 bit)
access : read-write

RXWINSZDEF : Default Rx Window size in us. Used when device a) is master connected b) performs its second receipt. 0 is not a valid value. Recommended value is 10.
bits : 4 - 11 (8 bit)
access : read-write

RWBLE_EN : 0: Disable BLE Core Exchange Table pre-fetch mechanism. 1: Enable BLE Core Exchange table pre-fetch mechanism.
bits : 8 - 16 (9 bit)
access : read-write

WLSYNC_EN : 0: WLAN synchronization pulse generation disabled 1: WLAN synchronization pulse generation enabled
bits : 9 - 18 (10 bit)
access : read-write

ADVERRFILT_EN : Advertising Channels Error Filtering Enable control 0: BLE Core reports all errors to BLE Software 1: BLE Core reports only correctly received packet, without error to BLE Software
bits : 10 - 20 (11 bit)
access : read-write

RXDESCPTRSEL : 0: Selects Rx Descriptor Pointer value from Control Structure 1: Selects Rx Descriptor Pointer value from CURRENTRXDESCPTR register
bits : 11 - 22 (12 bit)
access : read-write

TXWINOFFSEL : Applicable only if device is in Initiator mode 0: Window Offset field in CONNECT_REQ comes from Tx Data Buffer 1: Window Offset field in CONNECT_REQ comes from Event Controller processing and is replaced in real time by Packet Controller
bits : 12 - 24 (13 bit)
access : read-write

HOP_REMAP_DSB : 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled
bits : 16 - 32 (17 bit)
access : read-write

CRC_DSB : 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx
bits : 17 - 34 (18 bit)
access : read-write

WHIT_DSB : 0: Normal operation. Whitening enabled. 1: Whitening disabled.
bits : 18 - 36 (19 bit)
access : read-write

CRYPT_DSB : 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data.
bits : 19 - 38 (20 bit)
access : read-write

NESN_DSB : 0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptor value ignored in Rx, meaning that no SN error reported.
bits : 20 - 40 (21 bit)
access : read-write

SN_DSB : 0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptor value ignored in Rx, meaning that no SN error reported.
bits : 21 - 42 (22 bit)
access : read-write

MD_DSB : 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are
bits : 22 - 44 (23 bit)
access : read-write

SCAN_ABORT : Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 24 - 48 (25 bit)
access : read-write

ADVERT_ABORT : Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 25 - 50 (26 bit)
access : read-write

RFTEST_ABORT : Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested. 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.
bits : 26 - 52 (27 bit)
access : read-write

REG_SOFT_RST : Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 29 - 58 (30 bit)
access : read-write

MASTER_TGSOFT_RST : Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 30 - 60 (31 bit)
access : read-write

MASTER_SOFT_RST : Reset the complete system except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
bits : 31 - 62 (32 bit)
access : read-write

CSCNTINTSTAT : Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
bits : 0 - 0 (1 bit)
access : read-only

RXINTSTAT : Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending.
bits : 1 - 2 (2 bit)
access : read-only

SLPINTSTAT : Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
bits : 2 - 4 (3 bit)
access : read-only

EVENTINTSTAT : Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
bits : 3 - 6 (4 bit)
access : read-only

CRYPTINTSTAT : Masked Encryption/Decryption interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
bits : 4 - 8 (5 bit)
access : read-only

ERRORINTSTAT : Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending.
bits : 5 - 10 (6 bit)
access : read-only

GROSSTGTIMINTSTAT : Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 6 - 12 (7 bit)
access : read-only

FINETGTIMINTSTAT : Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
bits : 7 - 14 (8 bit)
access : read-only

RADIOCNTLINTSTAT : Radio Controller interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 8 - 16 (9 bit)
access : read-only

CSCNTINTRAWSTAT : 625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
bits : 0 - 0 (1 bit)
access : read-only

RXINTRAWSTAT : Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending.
bits : 1 - 2 (2 bit)
access : read-only

SLPINTRAWSTAT : Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
bits : 2 - 4 (3 bit)
access : read-only

EVENTINTRAWSTAT : End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
bits : 3 - 6 (4 bit)
access : read-only

CRYPTINTRAWSTAT : Encryption/Decryption interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
bits : 4 - 8 (5 bit)
access : read-only

ERRORINTRAWSTAT : Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending.
bits : 5 - 10 (6 bit)
access : read-only

GROSSTGTIMINTRAWSTAT : Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 6 - 12 (7 bit)
access : read-only

FINETGTIMINTRAWSTAT : Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
bits : 7 - 14 (8 bit)
access : read-only

RADIOCNTLINTRAWSTAT : Radio Controller interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
bits : 8 - 16 (9 bit)
access : read-only

CSCNTINTACK : 625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags.
bits : 0 - 0 (1 bit)
access : write-only

RXINTACK : Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags.
bits : 1 - 2 (2 bit)
access : write-only

SLPINTACK : End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags.
bits : 2 - 4 (3 bit)
access : write-only

EVENTINTACK : End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags.
bits : 3 - 6 (4 bit)
access : write-only

CRYPTINTACK : Encryption/Decryption interrupt acknowledgement bit Software writing 1 acknowledges the Encryption / Decryption interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags.
bits : 4 - 8 (5 bit)
access : write-only

ERRORINTACK : Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags.
bits : 5 - 10 (6 bit)
access : write-only

GROSSTGTIMINTACK : Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags.
bits : 6 - 12 (7 bit)
access : write-only

FINETGTIMINTACK : Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags.
bits : 7 - 14 (8 bit)
access : write-only

RADIOCNTLINTACK : Radio Controller interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets RADIOCNTLINTSTAT and RADIOCNTLINTRAWSTAT flags.
bits : 8 - 16 (9 bit)
access : write-only

BASETIMECNT : Value of the 625us base time reference counter. Updated each time BLE_SAMPLECLK_REG[SAMP] is written. Used by the SW in order to synchronize with the HW.
bits : 0 - 26 (27 bit)
access : read-only

FINECNT : Value of the current usec fine time reference counter. Updated each usec. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration
bits : 0 - 9 (10 bit)
access : read-only

EMACCERRSTAT : Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a 1 at EMACCERRACK bitfield. This bit will be set to 1 by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is 1 then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is 1 .
bits : 0 - 0 (1 bit)
access : read-only

EMACCERRACK : Exchange Memory Access Error Acknowledge. When the SW writes a 1 to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes 0 it will have no affect. The read value is always 0 .
bits : 1 - 2 (2 bit)
access : write-only

EMACCERRMSK : Exchange Memory Access Error Mask: When cleared to 0 the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to 1 an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is 1 .
bits : 2 - 4 (3 bit)
access : read-write

DIAGPORT_SEL : BLE/RADIO Diagnostic Port Selection. Controls the multiplexing of the internal diagnostic signals towards the 8-bit diagnostic bus DIAGPORT[7:0]. The DIAGPORT[7:0] bit order may or may not be reversed by using the DIAGPORT_REVERSE bitfield and then it will be directed to the GPIOs P0[7:0] and P1[3:0]. (Note that the P1[3:0] diagnostic signals are the same with P0[3:0] signals.) The DIAGPORT[7:0] value, depending on the DIAGPORT_SEL value, is: 00: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2:0]} 01: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2] , wakeup_lp_irq, deep_sleep_stat_32k} 10: RADIO_DIAG0[7:0] 11: RADIO_DIAG1[7:0]
bits : 3 - 7 (5 bit)
access : read-write

DIAGPORT_REVERSE : BLE/RADIO Diagnostic Port Reverse order. When this bit is 1 , the mapping of the diagnostic bus DIAGPORT[7:0] (controlled by DIAGPORT_SEL) to GPIOs (controlled by Pxy_MODE_REG[PID]) is reversed. The mapping is: If 0 then DIAGPORT[7] is mapped to P0[7], etc. DIAGPORT[4] is mapped to P0[4], DIAGPORT[3] is mapped to P0[3] and P1[3], etc. and DIAGPORT[0] is mapped to P0[0] and P1[0]. If 1 then DIAGPORT[7] is mapped to P0[0] and P1[0], etc. DIAGPORT[4] is mapped to P0[3] and P1[3], DIAGPORT[3] is mapped to P0[4], etc. and DIAGPORT[0] is mapped to P0[7].
bits : 5 - 10 (6 bit)
access : read-write

BLE_CLK_STAT : 0: BLE uses low power clock 1: BLE uses master clock
bits : 6 - 12 (7 bit)
access : read-only

MON_LP_CLK : The SW can only write a 0 to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to 1 . This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc.
bits : 7 - 14 (8 bit)
access : read-write

RADIO_PWRDN_ALLOW : This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to 0 when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted.
bits : 8 - 16 (9 bit)
access : read-only

BLE_CLK_SEL : BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBTLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBTLECONF_REG[CLK_SEL].
bits : 9 - 23 (15 bit)
access : read-write

RADIO_ONLY : Keep to 0.
bits : 17 - 34 (18 bit)
access : read-write

BB_ONLY : Keep to 0.
bits : 18 - 36 (19 bit)
access : read-write

SW_RPL_SPI : Keep to 0.
bits : 19 - 38 (20 bit)
access : read-write

WAKEUPLPSTAT : The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period.
bits : 20 - 40 (21 bit)
access : read-only

BLE_RSSI_SEL : 0: Select Peak-hold RSSI value (default). 1: Select current Average RSSI value.
bits : 21 - 42 (22 bit)
access : read-write

DIAGIRQ_MASK_0 : Diagnostic IRQ Mask 0 When set to 1 a BLE_RF_DIAG_IRQ will be generated on each rise of the DIAGIRQ_STAT_0 bit. When cleared to 0 no IRQ will be generated.
bits : 0 - 0 (1 bit)
access : read-write

DIAGIRQ_WSEL_0 : Diagnostic IRQ Word Select 0 Selects the 8-bit diagnostic bus that will be used for the IRQ generation. 00: Selects the BLE_DIAG0 01: Selects the BLE_DIAG1 10: Selects the RADIO_DIAG0 11: Selects the RADIO_DIAG1
bits : 1 - 3 (3 bit)
access : read-write

DIAGIRQ_BSEL_0 : Diagnostic IRQ Bit Select 0 Selects the bit of the 8-bit bus (as selected by the DIAGIRQ_WSEL_0) that will be used for the IRQ generation.
bits : 3 - 8 (6 bit)
access : read-write

DIAGIRQ_EDGE_0 : Diagnostic IRQ Edge 0 Selects the edge of the selected bit (refer to DIAGIRQ_BSEL_0) that will trigger the assertion of DIAGIRQ_STAT_0. If '0' then the positive edge is selected, when 1 the negative edge is selected.
bits : 6 - 12 (7 bit)
access : read-write

DIAGIRQ_STAT_0 : Diagnostic IRQ Status 0 This bit is read only. It is automatically cleared to 0 on each read of the BLE_RF_DIAGIRQ_REG register. It is automatically asserted to 1 on each detection of the selected edge, of the selected bit, of the selected word.
bits : 7 - 14 (8 bit)
access : read-only

DIAGIRQ_MASK_1 : Same as DIAGIRQ_MASK_0.
bits : 8 - 16 (9 bit)
access : read-write

DIAGIRQ_WSEL_1 : Same as DIAGIRQ_WSEL_0.
bits : 9 - 19 (11 bit)
access : read-write

DIAGIRQ_BSEL_1 : Same as DIAGIRQ_BSEL_0.
bits : 11 - 24 (14 bit)
access : read-write

DIAGIRQ_EDGE_1 : Same as DIAGIRQ_EDGE_0.
bits : 14 - 28 (15 bit)
access : read-write

DIAGIRQ_STAT_1 : Same as DIAGIRQ_STAT_0.
bits : 15 - 30 (16 bit)
access : read-only

DIAGIRQ_MASK_2 : Same as DIAGIRQ_MASK_0.
bits : 16 - 32 (17 bit)
access : read-write

DIAGIRQ_WSEL_2 : Same as DIAGIRQ_WSEL_0.
bits : 17 - 35 (19 bit)
access : read-write

DIAGIRQ_BSEL_2 : Same as DIAGIRQ_BSEL_0.
bits : 19 - 40 (22 bit)
access : read-write

DIAGIRQ_EDGE_2 : Same as DIAGIRQ_EDGE_0.
bits : 22 - 44 (23 bit)
access : read-write

DIAGIRQ_STAT_2 : Same as DIAGIRQ_STAT_0.
bits : 23 - 46 (24 bit)
access : read-only

DIAGIRQ_MASK_3 : Same as DIAGIRQ_MASK_0.
bits : 24 - 48 (25 bit)
access : read-write

DIAGIRQ_WSEL_3 : Same as DIAGIRQ_WSEL_0.
bits : 25 - 51 (27 bit)
access : read-write

DIAGIRQ_BSEL_3 : Same as DIAGIRQ_BSEL_0.
bits : 27 - 56 (30 bit)
access : read-write

DIAGIRQ_EDGE_3 : Same as DIAGIRQ_EDGE_0.
bits : 30 - 60 (31 bit)
access : read-write

DIAGIRQ_STAT_3 : Same as DIAGIRQ_STAT_0.
bits : 31 - 62 (32 bit)
access : read-only

BDADDRL : Bluetooth Low Energy Device Address. LSB part.
bits : 0 - 31 (32 bit)
access : read-write

BDADDRU : Bluetooth Low Energy Device Address. MSB part.
bits : 0 - 15 (16 bit)
access : read-write

PRIV_NPUB : Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address
bits : 16 - 32 (17 bit)
access : read-write

CURRENTRXDESCPTR : Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List.
bits : 0 - 13 (14 bit)
access : read-write

DEEP_SLEEP_IRQ_EN : Always set to 3 when DEEP_SLEEP_ON is set to 1 . It controls the generation of BLE_WAKEUP_LP_IRQ.
bits : 0 - 1 (2 bit)
access : read-write

DEEP_SLEEP_ON : 0: BLE Core in normal active mode 1: Request BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge.
bits : 2 - 4 (3 bit)
access : read-write

DEEP_SLEEP_CORR_EN : 625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Always read as 0. No action happens if it is written with 0.
bits : 3 - 6 (4 bit)
access : read-write

SOFT_WAKEUP_REQ : Wake Up Request from BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the BLE Core when written with a 1. Always read as 0. No action happens if it is written with 0.
bits : 4 - 8 (5 bit)
access : read-write

DEEP_SLEEP_STAT : Indicator of current Deep Sleep clock mux status: 0: BLE Core is not yet in Deep Sleep Mode 1: BLE Core is in Deep Sleep Mode (only Low Power Clock is running)
bits : 15 - 30 (16 bit)
access : read-only

EXTWKUPDSB : External Wake-Up disable 0: BLE Core can be woken by external wake-up 1: BLE Core cannot be woken up by external wake-up
bits : 31 - 62 (32 bit)
access : read-write

DEEPSLTIME : Determines the time in Low Power Clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz. If DEEPSLTIME is set to zero, the Deep Sleep Time duration is considered as infinite, and only wake up requests can restore active behaviour BLE Software must ensure DEEPSLTIME value to be greater than 2 in order to cope with control resynchronization requirements
bits : 0 - 31 (32 bit)
access : read-write

DEEPSLDUR : Actual duration of the last deep sleep phase measured in Low Power Clock cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each Low Power Clock cycle until the end of the deep sleep phase.
bits : 0 - 31 (32 bit)
access : read-only

TWIRQ_RESET : Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz [0...31.25 ms] for 32.768kHz.
bits : 0 - 9 (10 bit)
access : read-write

TWIRQ_SET : Minimum value is TWIRQ_RESET + 1 . Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
bits : 10 - 30 (21 bit)
access : read-write

TWEXT : Minimum and recommended value is TWIRQ_RESET + 1 . In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
bits : 21 - 52 (32 bit)
access : read-write

BUILD : BLE Core Build - Build number
bits : 0 - 7 (8 bit)
access : read-only

UPG : BLE Core upgrade - Upgrade number. (Correspond to FS v1.11)
bits : 8 - 23 (16 bit)
access : read-only

REL : BLE Core version - Major release number.(Correspond to FS v1.11)
bits : 16 - 39 (24 bit)
access : read-only

TYP : BLE Core Type - 0x6 means BT4.0 (i.e correspond LL version assigned number)
bits : 24 - 55 (32 bit)
access : read-only

FINECNTCORR : Phase correction value for the 625usec reference counter (i.e Fine Counter) in us.
bits : 0 - 9 (10 bit)
access : read-write

BASETIMECNTCORR : Base Time Counter correction value.
bits : 0 - 26 (27 bit)
access : read-write

DIAG0 : Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port 0.
bits : 0 - 5 (6 bit)
access : read-write

DIAG0_EN : 0: Disable diagnostic port 0 output. All outputs are set to 0. 1: Enable diagnostic port 0 output.
bits : 7 - 14 (8 bit)
access : read-write

DIAG1 : Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port 1.
bits : 8 - 21 (14 bit)
access : read-write

DIAG1_EN : 0: Disable diagnostic port 1 output. All outputs are set to 0. 1: Enable diagnostic port 1 output.
bits : 15 - 30 (16 bit)
access : read-write

DIAG2 : Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port 2.
bits : 16 - 37 (22 bit)
access : read-write

DIAG2_EN : 0: Disable diagnostic port 2 output. All outputs are set to 0. 1: Enable diagnostic port 2 output.
bits : 23 - 46 (24 bit)
access : read-write

DIAG3 : Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port 3.
bits : 24 - 53 (30 bit)
access : read-write

DIAG3_EN : 0: Disable diagnostic port 3 output. All outputs are set to 0. 1: Enable diagnostic port 3 output.
bits : 31 - 62 (32 bit)
access : read-write

DIAG0STAT : Directly connected to ble_dbg0[7:0] output. Debug use only.
bits : 0 - 7 (8 bit)
access : read-only

DIAG1STAT : Directly connected to ble_dbg1[7:0] output. Debug use only.
bits : 8 - 23 (16 bit)
access : read-only

DIAG2STAT : Directly connected to ble_dbg2[7:0] output. Debug use only.
bits : 16 - 39 (24 bit)
access : read-only

DIAG3STAT : Directly connected to ble_dbg3[7:0] output. Debug use only.
bits : 24 - 55 (32 bit)
access : read-only

ADDMAX : Upper limit for the memory zone.
bits : 0 - 15 (16 bit)
access : read-write

ADDMIN : Lower limit for the memory zone.
bits : 0 - 15 (16 bit)
access : read-write

TXCRYPT_ERROR : Real Time Encryption Error, happens when encryption is not finished before Tx Payload has to be sent 0: No error 1: Error occurred
bits : 0 - 0 (1 bit)
access : read-only

PKTCNTL_EMACC_ERROR : Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred
bits : 1 - 2 (2 bit)
access : read-only

TXDESC_ERROR : Tx Descriptor Error, happens when fetched Tx Descriptor has TXDONE bit not set 0: No error 1: Error occurred
bits : 2 - 4 (3 bit)
access : read-only

APFM_ERROR : Anticipated Pre-Fetch Mechanism error, happens when 3 consecutive Exchange Table entry have been programmed, 0: no error 1: Error occured
bits : 3 - 6 (4 bit)
access : read-only

WHITELIST_ERROR : White List Timeout Error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred
bits : 4 - 8 (5 bit)
access : read-only

RXCRYPT_ERROR : Real Time Decryption Error, happens when decryption is not finished before IFS time 0: No error 1: Error occurred
bits : 5 - 10 (6 bit)
access : read-only

IFS_UNDERRUN : Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred
bits : 6 - 12 (7 bit)
access : read-only

LLCHMAP_ERROR : Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred
bits : 7 - 14 (8 bit)
access : read-only

RADIO_EMACC_ERROR : Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted. 0: No error 1: Error occurred
bits : 8 - 16 (9 bit)
access : read-only

CSTXPTR_ERROR : Indicates whether CS-TXPTR is null, this is a major software programming failure. 0: No error 1: Error occurred
bits : 10 - 20 (11 bit)
access : read-only

CSFORMAT_ERROR : Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred
bits : 11 - 22 (12 bit)
access : read-only

SWPROFVAL : Software Profiling register: used by BLE Software for profiling purpose: this value is copied on Diagnostic port
bits : 0 - 31 (32 bit)
access : read-write

DPCORR_EN : Enable the use of delayed DC compensated data path in Radio Correlator block 1: Enable 0: Disable Must be set to 0 .
bits : 22 - 44 (23 bit)
access : read-write

XRFSEL : Extended radio selection field, Must be set to '00011'.
bits : 16 - 36 (21 bit)
access : read-write

BUSWIDTH : Processor bus width: 0: 16 bits 1: 32 bits
bits : 0 - 0 (1 bit)
access : read-only

USECRYPT : 0: Encryption block not present 1: Encryption block present
bits : 1 - 2 (2 bit)
access : read-only

USEDBG : 0: Diagnostic port not instantiated 1: Diagnostic port instantiated
bits : 2 - 4 (3 bit)
access : read-only

WLAN : 0: WLAN Coexistence mechanism not present 1: WLAN Coexistence mechanism present
bits : 3 - 6 (4 bit)
access : read-only

INTMODE : 0: Interrupts are edge level generated, i.e pulse. 1: Interrupts are trigger level generated, i.e stays active at 1 till acknowledgement
bits : 4 - 8 (5 bit)
access : read-only

DMMODE : 0: BLE Core is used as a standalone BLE device 1: BLE Core is used in a Dual Mode device
bits : 5 - 10 (6 bit)
access : read-only

CLK_SEL : Operating Frequency (in MHz). This field is a copy of the BLE_CNTL2_REG[BLE_CLK_SEL] value.
bits : 8 - 21 (14 bit)
access : read-only

RFIF : Supported radio interfaces. 0001000: on-chip radio others: reserved
bits : 16 - 38 (23 bit)
access : read-only

ADD_WIDTH : Value of the BLE_ADDRESS_WIDTH parameter converted into binary.
bits : 24 - 53 (30 bit)
access : read-only

TXPWRUP : This register holds the length in us of the Tx power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends of the selected radio.
bits : 0 - 7 (8 bit)
access : read-write

TXPWRDN : This register extends the length in us of the Tx power down phase for the current radio device. Default value is 3us (reset value). Operating range depends of the selected radio.
bits : 8 - 19 (12 bit)
access : read-write

RXPWRUP : This register holds the length in us of the Rx power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends of the selected radio.
bits : 16 - 39 (24 bit)
access : read-write

RTRIP_DELAY : Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us.
bits : 24 - 54 (31 bit)
access : read-write

ADVCHMAP : Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37.
bits : 0 - 2 (3 bit)
access : read-write

ADVINT : Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in usec. Value to program depends of the used Advertising Packet type and the device filtering policy. Please refer to Table 3-10 for details about ADVINT programming range.
bits : 0 - 13 (14 bit)
access : read-write

UPPERLIMIT : Active scan mode upper limit counter value.
bits : 0 - 8 (9 bit)
access : read-write

BACKOFF : Active scan mode back-off counter initialization value.
bits : 16 - 40 (25 bit)
access : read-write

WLPUBADDPTR : Start address pointer of the public devices white list.
bits : 0 - 15 (16 bit)
access : read-write

WLPRIVADDPTR : Start address pointer of the private devices white list.
bits : 0 - 15 (16 bit)
access : read-write

NBPUBDEV : Number of public devices in the white list.
bits : 0 - 7 (8 bit)
access : read-write

NBPRIVDEV : Number of private devices in the white list.
bits : 8 - 23 (16 bit)
access : read-write

CSCNTINTMSK : 625usec Base Time Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 0 - 0 (1 bit)
access : read-write

RXINTMSK : Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 1 - 2 (2 bit)
access : read-write

SLPINTMSK : Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 2 - 4 (3 bit)
access : read-write

EVENTINTMSK : End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 3 - 6 (4 bit)
access : read-write

CRYPTINTMSK : Encryption / Decryption Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 4 - 8 (5 bit)
access : read-write

ERRORINTMSK : Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
bits : 5 - 10 (6 bit)
access : read-write

GROSSTGTIMINTMSK : Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated
bits : 6 - 12 (7 bit)
access : read-write

FINETGTIMINTMSK : Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated
bits : 7 - 14 (8 bit)
access : read-write

RADIOCNTLINTMSK : Radio Controller interrupt mask 0: Interrupt not generated 1: Interrupt generated
bits : 8 - 16 (9 bit)
access : read-write

CSCNTDEVMSK : CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events.
bits : 15 - 30 (16 bit)
access : read-write

INTCSCNTL : Selection of the CS counter that generates an interrupt. For example, if INTCNTL[3] is set, an interrupt is sent each time CS counter equals 3.
bits : 16 - 47 (32 bit)
access : read-write

AES_START : Writing a 1 starts AES-128 ciphering process. This bit is reset once the process is finished (i.e BLE_CRYPT_IRQ interrupt occurs, even masked)
bits : 0 - 0 (1 bit)
access : read-write

AESKEY31_0 : AES encryption 128-bit key. Bit 31 down to 0
bits : 0 - 31 (32 bit)
access : read-write

AESKEY63_32 : AES encryption 128-bit key. Bit 63 down to 32
bits : 0 - 31 (32 bit)
access : read-write

AESKEY95_64 : AES encryption 128-bit key. Bit 95 down to 64
bits : 0 - 31 (32 bit)
access : read-write

AESKEY127_96 : AES encryption 128-bit key. Bit 127 down to 96
bits : 0 - 31 (32 bit)
access : read-write

AESPTR : Pointer to the memory zone where the block to encrypt/decrypt is stored.
bits : 0 - 15 (16 bit)
access : read-write

TXMICVAL : AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ interrupt (even masked)
bits : 0 - 31 (32 bit)
access : read-only

RXMICVAL : AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ interrupt (even masked)
bits : 0 - 31 (32 bit)
access : read-only