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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection :

Registers

DCDC_CTRL_REG

DCDC_CTRL2_REG

DCDC_CTRL3_REG


DCDC_CTRL_REG

DCDC control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDC_CTRL_REG DCDC_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VBAT1V_LEV DCDC_MODE DCDC_DRIVE_NSW DCDC_DRIVE_PSW DCDC_DRIVE_OSW DCDC_TUNE

DCDC_VBAT1V_LEV : If VBAT1V is below this level, the boost converter will be disabled: 110 = 0.6V 101 = 0.8V 011 = 1.0V 111 = 0V (always OK)
bits : 1 - 4 (4 bit)
access : read-write

DCDC_MODE : Testmodes, keep 000.
bits : 5 - 12 (8 bit)
access : read-write

DCDC_DRIVE_NSW : Drive level of the switch between SWITCH and GROUND. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
bits : 8 - 17 (10 bit)
access : read-write

DCDC_DRIVE_PSW : Drive level of the switch between SWITCH and VBAT3V. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
bits : 10 - 21 (12 bit)
access : read-write

DCDC_DRIVE_OSW : Drive level of the switch between SWITCH and VDCDC. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
bits : 12 - 25 (14 bit)
access : read-write

DCDC_TUNE : Tune-bits to compensate for parasitic resistance in the current sense circuit of the DCDC-converter.
bits : 14 - 29 (16 bit)
access : read-write


DCDC_CTRL2_REG

DCDC second control register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDC_CTRL2_REG DCDC_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_AUTO_CAL DCDC_CUR_LIM DCDC_TON DCDC_VBAT3V_LEV DCDC_VOLT_LEV

DCDC_AUTO_CAL : Control of the automatic calibration of the DCDC-converter. For Buck-mode use 0x1, for Boost-mode use 0x6. Automatic calibration is disabled by setting 0x0
bits : 0 - 2 (3 bit)
access : read-write

DCDC_CUR_LIM : Current limit in the switches of the DCDC-converter (approximate values): N x 10mA
bits : 3 - 9 (7 bit)
access : read-write

DCDC_TON : This defines the minimum on-time of the comparators. For buck-mode use 0x2, for boost-mode use 0x1
bits : 7 - 15 (9 bit)
access : read-write

DCDC_VBAT3V_LEV : Nominal VBAT3V output voltage of the boost converter. 000 ... 011 = 1.8V + N*25mV 100 = 2.4V 101 = 2.5V 110 = 2.62V 111 = 2.76V (Note: MSB is automatically on if the OTP LDO is enabled.)
bits : 9 - 20 (12 bit)
access : read-write

DCDC_VOLT_LEV : Nominal output voltage of the DCDC-converter. VDCDC = 1.2V + N*25mV
bits : 12 - 27 (16 bit)
access : read-write


DCDC_CTRL3_REG

DCDC thirth control register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDC_CTRL3_REG DCDC_CTRL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCK_ENABLE DCDC_IDLE_CLK DCDC_TIMEOUT

BUCK_ENABLE : Enables the buck converter when the device becomes active and VBAT1V is connected to GND.
bits : 0 - 0 (1 bit)
access : read-write

DCDC_IDLE_CLK : Clock used as trigger for the idle state to check voltage. (Note: when no 16 MHz oscillator is active, the 32 kHz oscillator will be used as trigger independent of the setting below:) 00 = 16 MHz 01 = 4 MHz 10 = 1 MHz 11 = 250 kHz
bits : 1 - 3 (3 bit)
access : read-write

DCDC_TIMEOUT : timeout for the idle state to check voltage
bits : 3 - 7 (5 bit)
access : read-write



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