OTPC_MODE_REG

OTPC_CELADR_REG

OTPC_NWORDS_REG

OTPC_FFPRT_REG

OTPC_FFRD_REG

OTPC_PCTRL_REG

OTPC_STAT_REG

OTPC_AHBADR_REG

OTPC_MODE_MODE : Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 000 - STBY mode 001 - MREAD mode 010 - MPROG mode 011 - AREAD mode 100 - APROG mode 101 - Test mode. Reserved 110 - Test mode. Reserved 111 - Test mode. Reserved To manually move between modes, always return to STBY mode first.
bits : 0 - 2 (3 bit)
access : read-write

OTPC_MODE_USE_DMA : Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG. 0 - DMAis not used. The data should be transfered from/to controller through OTPC_FFPRT_REG 1 - DMA is used. Data transfers from/to controller are performed automatically. The AHB base address should be configured in OTPC_AHBADR_REG before the selection of the mode. If programming of the OTPC_MODE_REG is performed through the serial interface,the OTPC_MODE_USE_DMA will be set to 0 automatically. If the controller is in APROG mode and the OTPC_MODE_PRG_PORT_SEL is enabled, the dma will stay inactive.
bits : 4 - 8 (5 bit)
access : read-write

OTPC_MODE_FIFO_FLUSH : Writing 1, removes any content from the FIFO. This bit returns automatically to 0.
bits : 5 - 10 (6 bit)
access : read-write

OTPC_MODE_TWO_CC_ACC : Defines the duration of each read from the OTP macrocells. 0 - Reads 16 bits of data every one clock cycle. 1 - Reads 16 bits of data every two clock cycles.
bits : 6 - 12 (7 bit)
access : read-write

OTPC_MODE_PRG_PORT_SEL : Selects an alternative data source for the programming of the OTP macrocells, when the controller is configured in APROG mode. 0 - The fifo will be used as the data source. The fifo will be filled with a way defined by the register OTPC_MODE_USE_DMA. The number of words that will be programmed is defined by OTPC_NWORDS. 1 - Only one word will programmed. The value of the word is contained in the prg_port port of the controller. The values of the registers OTPC_MODE_USE_DMA, OTPC_NWORDS and the contents of the FIFO will not be used.
bits : 7 - 14 (8 bit)
access : read-write

OPTC_MODE_PRG_FAST : Defines the timing that will be used for all the programming activities (APROG, MPROG and TWR) 0 - Selects the normal timing 1 - Selects the fast timing
bits : 8 - 16 (9 bit)
access : read-write

OTPC_MODE_PRG_PORT_MUX : Selects the source that is connected to the prg_port port of the controller. 00 - {16'd0, BANDGAP_REG[15:0]} 01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0, RFIO_CTRL1_REG{7:0]} 10 - {3'd0, RF_LNA_CTRL3_REG[4:0], RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]} 11 - {28'd0, RF_VCO_CTRL_REG[3:0]} See OTPC_MODE_PRG_PORT_SEL about the use of the prg_port
bits : 28 - 57 (30 bit)
access : read-write

OTPC_CELADR : Defines a word address inside the macrocell. Used in modes AREAD and APROG and is automatically updated.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_NWORDS : The number of words (minus one) for reading/programming during the AREAD/APROG mode. If in APROG mode, and the OTPC_MODE_PRG_PORT_SEL is enabled (=1), this register will not be used and will stay unchanged. During mirroring, this register reflects the current amount of data that will be copied. It keeps its value until be written by the software with a new value. The number of the words that remaining to be processed by the controller is contained in the field OTPC_STAT_NWORDS.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_FFPRT : Provides access to the fifo through an access port. Write this register with the corresponding data, when the APROG mode is selected and the DMA is disabled. Read from this register the corresponding data, when the AREAD mode is selected and the DMA is disabled. Check OTPC_STAT_FWORDS register for data/space availability, before accessing the fifo.
bits : 0 - 31 (32 bit)
access : read-write

OTPC_FFRD : Contains the value read from the fifo, after a read of the OTPC_FFPRT_REG register.
bits : 0 - 31 (32 bit)
access : read-only

OTPC_PCTRL_WADDR : Defines the address of a 32 bits word {U1,L1,U0,L0} in the macrocells, where one or two bits will be programmed. There are two macrocell banks, with 8 bits each. Each bank contribute with two memory positions for each 32 bits word. The Ux, Lx represent the bytes of the upper and lower bank respectively.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_PCTRL_BADRL : Selects the bit inside the Lx (x=0,1) byte, which will be programmed in the lower bank.
bits : 16 - 34 (19 bit)
access : read-write

OTPC_PCTRL_BSELL : Selects between the L1 and L0 byte for the programming sequence in the lower bank. 0 - Program the L0 byte 1 - Program the L1 byte
bits : 19 - 38 (20 bit)
access : read-write

OTPC_PCTRL_BADRU : Selects the bit inside the Ux (x=0,1) byte, which will be programmed in the upper bank.
bits : 20 - 42 (23 bit)
access : read-write

OTPC_PCTRL_BSELU : Selects between the U1 and U0 byte for the programming sequence in the upper bank. 0 - Program the U0 byte 1 - Program the U1 byte -
bits : 23 - 46 (24 bit)
access : read-write

OTPC_PCTRL_BITL : Defines the value of the selected bit in the lower bank, after the programming sequence.
bits : 24 - 48 (25 bit)
access : read-write

OTPC_PCTRL_ENL : Enables the programming in the lower bank. 0 - The programming sequence is not applied in the lower bank. 1 -The programming sequence is applied in the lower bank.
bits : 25 - 50 (26 bit)
access : read-write

OTPC_PCTRL_BITU : Defines the value of the selected bit in the upper bank, after the programming sequence.
bits : 26 - 52 (27 bit)
access : read-write

OTPC_PCTRL_ENU : Enables the programming in the upper bank of the OTP. 0 - Programming sequence is not applied in the upper bank. 1 - Programming sequence is applied in the upper bank.
bits : 27 - 54 (28 bit)
access : read-write

OTPC_STAT_PRDY : Indicates the state of a bit-programming process. 0 - The controller is busy. A bit-programming is in progress 1 - The logic which performs bit-programming is idle. When the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request. During APROG mode, the value of this field it is normal to changing periodically.
bits : 0 - 0 (1 bit)
access : read-only

OTPC_STAT_PERROR : Indicates that an error has occurred during the bit-programming process. 0 - No error during the bit-programming process. 1 - The process of bit-programming failed. When the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY= 1). During APROG mode, the value of this field is normal to change periodically. Upon finishing the operation in the APROG mode (OTPC_STAT_ARDY= 1), this field indicates if the programming has failed or ended succesfully.
bits : 1 - 2 (2 bit)
access : read-only

OTPC_STAT_TRDY : Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes. 0 - The controller is busy. A test mode is in progress. 1 - There is no active test mode.
bits : 2 - 4 (3 bit)
access : read-only

OTPC_STAT_TERROR : Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY= 1). 0 - The test sequence ends with no error. 1 - The test sequence has failed.
bits : 3 - 6 (4 bit)
access : read-only

OTPC_STAT_ARDY : Monitors the progress of read or programming operations while in the AREAD or APROG modes. 0 - The controller is busy while reading or programming (AREAD or APROG modes). 1 - The controller is not busy in AREAD or APROG mode.
bits : 4 - 8 (5 bit)
access : read-only

OTPC_STAT_FWORDS : Indicates the number of words which contained in the fifo of the controller.
bits : 8 - 19 (12 bit)
access : read-only

OTPC_STAT_PERR_L : Indicates the lower bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the lower bank 1 - A programming error has occured in the lower bank
bits : 12 - 24 (13 bit)
access : read-only

OTPC_STAT_PERR_U : Indicates the upper bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the upper bank 1 - A programming error has occured in the upper bank
bits : 13 - 26 (14 bit)
access : read-only

OTPC_STAT_TERR_L : Indicates the lower bank as the source of a test error. The value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the lower bank 1 - A test error has occured in the lower bank
bits : 14 - 28 (15 bit)
access : read-only

OTPC_STAT_TERR_U : Indicates the upper bank as the source of a test error. This value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the upper bank 1 - A test error has occured in the upper bank
bits : 15 - 30 (16 bit)
access : read-only

OTPC_STAT_NWORDS : Contains the current value of the words to be processed.
bits : 16 - 44 (29 bit)
access : read-only

OTPC_AHBADR : Tthe AHB address used by the AHB master interface of the controller ( bits [31:2]).
bits : 2 - 33 (32 bit)
access : read-write