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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x12 byte (0x0)
mem_usage : registers
protection :

Registers

TIMER0_CTRL_REG

TRIPLE_PWM_CTRL_REG

TIMER0_ON_REG

TIMER0_RELOAD_M_REG

TIMER0_RELOAD_N_REG

PWM2_DUTY_CYCLE

PWM3_DUTY_CYCLE

PWM4_DUTY_CYCLE

TRIPLE_PWM_FREQUENCY


TIMER0_CTRL_REG

Timer0 control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CTRL_REG TIMER0_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_CTRL TIM0_CLK_SEL TIM0_CLK_DIV PWM_MODE

TIM0_CTRL : 0 = Timer0 is off and in reset state. 1 = Timer0 is running.
bits : 0 - 0 (1 bit)
access : read-write

TIM0_CLK_SEL : 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses 32 kHz (slow) clock frequency.
bits : 1 - 2 (2 bit)
access : read-write

TIM0_CLK_DIV : 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter.
bits : 2 - 4 (3 bit)
access : read-write

PWM_MODE : 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz.
bits : 3 - 6 (4 bit)
access : read-write


TRIPLE_PWM_CTRL_REG

PWM 2 3 4 Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_CTRL_REG TRIPLE_PWM_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIPLE_PWM_ENABLE SW_PAUSE_EN HW_PAUSE_EN

TRIPLE_PWM_ENABLE : '1' = PWM 2 3 4 is enabled
bits : 0 - 0 (1 bit)
access : read-write

SW_PAUSE_EN : '1' = PWM 2 3 4 is paused
bits : 1 - 2 (2 bit)
access : read-write

HW_PAUSE_EN : '1' = HW can pause PWM 2,3,4
bits : 2 - 4 (3 bit)
access : read-write


TIMER0_ON_REG

Timer0 on control register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_ON_REG TIMER0_ON_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_ON

TIM0_ON : Timer0 On reload value: If read the actual counter value ON_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


TIMER0_RELOAD_M_REG

16 bits reload value for Timer0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_RELOAD_M_REG TIMER0_RELOAD_M_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_M

TIM0_M : Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


TIMER0_RELOAD_N_REG

16 bits reload value for Timer0
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_RELOAD_N_REG TIMER0_RELOAD_N_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_N

TIM0_N : Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


PWM2_DUTY_CYCLE

Duty Cycle for PWM2
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2_DUTY_CYCLE PWM2_DUTY_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY_CYCLE

DUTY_CYCLE : duty cycle for PWM
bits : 0 - 13 (14 bit)
access : read-write


PWM3_DUTY_CYCLE

Duty Cycle for PWM3
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3_DUTY_CYCLE PWM3_DUTY_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY_CYCLE

DUTY_CYCLE : duty cycle for PWM
bits : 0 - 13 (14 bit)
access : read-write


PWM4_DUTY_CYCLE

Duty Cycle for PWM4
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM4_DUTY_CYCLE PWM4_DUTY_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUTY_CYCLE

DUTY_CYCLE : duty cycle for PWM
bits : 0 - 13 (14 bit)
access : read-write


TRIPLE_PWM_FREQUENCY

Frequency for PWM 2,3 and 4
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_FREQUENCY TRIPLE_PWM_FREQUENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ

FREQ : Freq for PWM 2 3 4
bits : 0 - 13 (14 bit)
access : read-write



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