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SCB_GROUP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x29 byte (0x0)
mem_usage : registers
protection :

Registers

CPUID

SCR

CCR

SHPR2

SHPR3

ICSR

AIRCR


CPUID

CPUID base register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVISION PARTNO CONSTANT VARIANT IMPLEMENTER

REVISION : REVISION[3:0] bits (Revision number)
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : PARTNO[11:0] bits (Part number of the processor core)
bits : 4 - 19 (16 bit)
access : read-only

CONSTANT : CONSTANT[3:0] bits (Reads as 0xF)
bits : 16 - 35 (20 bit)
access : read-only

VARIANT : VARIANT[3:0] bits (Variant number)
bits : 20 - 43 (24 bit)
access : read-only

IMPLEMENTER : IMPLEMENTER[7:0] bits (Implementer code)
bits : 24 - 55 (32 bit)
access : read-only


SCR

System control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVEONPEND

SLEEPONEXIT : Configures sleep-on-exit when returning from Handler mode to Thread mode
bits : 1 - 2 (2 bit)
access : read-write

SLEEPDEEP : Controls whether the processor uses sleep or deep sleep
bits : 2 - 4 (3 bit)
access : read-write

SEVEONPEND : Send event on pending bit
bits : 4 - 8 (5 bit)
access : read-write


CCR

Configuration and control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNALIGN_TRP STKALIGN

UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 6 (4 bit)
access : read-write

STKALIGN : Configures stack alignment on exception entry
bits : 9 - 18 (10 bit)
access : read-write


SHPR2

System handler priority register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR2 SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : PRI_11[7:0] bits (Priority of system handler 11, SVCall)
bits : 24 - 55 (32 bit)
access : read-write


SHPR3

System handler priority register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR3 SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : PRI_14[7:0] bits (Priority of system handler 14, PendSV)
bits : 16 - 39 (24 bit)
access : read-write

PRI_15 : PRI_15[7:0] bits (Priority of system handler 15, SysTick exception)
bits : 24 - 55 (32 bit)
access : read-write


ICSR

Interrupt control and state register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE VECTPENDING ISRPENDING PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : VECTACTIVE[5:0] bits (Active vector)
bits : 0 - 5 (6 bit)
access : read-write

VECTPENDING : VECTPENDING[5:0] bits (Pending vector)
bits : 12 - 29 (18 bit)
access : read-write

ISRPENDING : Interrupt pending flag, excluding NMI and Faults
bits : 22 - 44 (23 bit)
access : read-write

PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 50 (26 bit)
access : read-write

PENDSTSET : SysTick exception set-pending bit
bits : 26 - 52 (27 bit)
access : read-write

PENDSVCLR : PendSV clear-pending bit
bits : 27 - 54 (28 bit)
access : read-write

PENDSVSET : PendSV set-pending bit
bits : 28 - 56 (29 bit)
access : read-write

NMIPENDSET : NMI set-pending bit
bits : 31 - 62 (32 bit)
access : read-write


AIRCR

Application interrupt and reset control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AIRCR AIRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTRESET VECTCLRACTIVE SYSRESETREQ ENDIANESS VECTKEY

VECTRESET : Reserved for Debug use
bits : 0 - 0 (1 bit)
access : read-only

VECTCLRACTIVE : Reserved for Debug use
bits : 1 - 2 (2 bit)
access : read-only

SYSRESETREQ : System reset request
bits : 2 - 4 (3 bit)
access : read-only

ENDIANESS : Data endianness bit
bits : 15 - 30 (16 bit)
access : read-only

VECTKEY : VECTKEY[15:0] bits (Register key)
bits : 16 - 47 (32 bit)
access : read-only



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