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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

GP_ADC_CTRL_REG

GP_ADC_CTRL2_REG

GP_ADC_OFFP_REG

GP_ADC_OFFN_REG

GP_ADC_CLEAR_INT_REG

GP_ADC_RESULT_REG

GP_ADC_DELAY_REG

GP_ADC_DELAY2_REG


GP_ADC_CTRL_REG

General Purpose ADC Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_CTRL_REG GP_ADC_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_EN GP_ADC_START GP_ADC_TEST GP_ADC_CLK_SEL GP_ADC_INT GP_ADC_MINT GP_ADC_SEL GP_ADC_SIGN GP_ADC_SE GP_ADC_MUTE GP_ADC_CHOP GP_ADC_LDO_EN GP_ADC_LDO_ZERO

GP_ADC_EN : 0 = ADC is disabled and in reset. 1 = ADC is enabled and sampling of input is started.
bits : 0 - 0 (1 bit)
access : read-write

GP_ADC_START : 0 = ADC conversion ready. 1 = If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set.
bits : 1 - 2 (2 bit)
access : read-write

GP_ADC_TEST : Reserved, keep 0.
bits : 2 - 4 (3 bit)

GP_ADC_CLK_SEL : 0 = Internal high-speed ADC clock used. 1 = Digital clock used.
bits : 3 - 6 (4 bit)
access : read-write

GP_ADC_INT : 1 = AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG.
bits : 4 - 8 (5 bit)
access : read-only

GP_ADC_MINT : 0 = Disable (mask) GP_ADC_INT. 1 = Enable GP_ADC_INT to ICU.
bits : 5 - 10 (6 bit)
access : read-write

GP_ADC_SEL : ADC input selection which must be set before the GP_ADC_START bit is enabled. If GP_ADC_SE = 1 (single ended mode): 0000 = P0[0] 0001 = P0[1] 0010 = P0[2] 0011 = P0[3] 0100 = AVS 0101 = VDD_REF 0110 = VDD_RTT (=VDD_REF) 0111 = VBAT3V 1000 = VDCDC 1001 = VBAT1V All other combinations are reserved. If GP_ADC_SE = 0 (differential mode): 0000 = P0[0] vs P0[1] All other combinations are P0[2] vs P0[3].
bits : 6 - 15 (10 bit)
access : read-write

GP_ADC_SIGN : 0 = Default 1 = Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency
bits : 10 - 20 (11 bit)
access : read-write

GP_ADC_SE : 0 = Differential mode 1 = Single ended mode
bits : 11 - 22 (12 bit)
access : read-write

GP_ADC_MUTE : Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC).
bits : 12 - 24 (13 bit)
access : read-write

GP_ADC_CHOP : Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements.
bits : 13 - 26 (14 bit)
access : read-write

GP_ADC_LDO_EN : Turns on LDO.
bits : 14 - 28 (15 bit)
access : read-write

GP_ADC_LDO_ZERO : Forces LDO-output to 0V.
bits : 15 - 30 (16 bit)
access : read-write


GP_ADC_CTRL2_REG

General Purpose ADC Second Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_CTRL2_REG GP_ADC_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_DELAY_EN GP_ADC_ATTN3X GP_ADC_IDYN GP_ADC_I20U

GP_ADC_DELAY_EN : Enables delay function for several signals. This is not auto-cleared. Toggle this bit before every sampling to enable succesive conversions.
bits : 0 - 0 (1 bit)
access : read-write

GP_ADC_ATTN3X : 0 = Input voltages up to 1.2V allowed. 1 = Input voltages up to 3.6V allowed by enabling 3x attenuator.
bits : 1 - 2 (2 bit)
access : read-write

GP_ADC_IDYN : Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
bits : 2 - 4 (3 bit)
access : read-write

GP_ADC_I20U : Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
bits : 3 - 6 (4 bit)
access : read-write


GP_ADC_OFFP_REG

General Purpose ADC Positive Offset Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_OFFP_REG GP_ADC_OFFP_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_OFFP

GP_ADC_OFFP : Offset adjust of 'positive' array of ADC-network (effective if 'GP_ADC_SE=0', or 'GP_ADC_SE=1 AND GP_ADC_SIGN=0')
bits : 0 - 9 (10 bit)
access : read-write


GP_ADC_OFFN_REG

General Purpose ADC Negative Offset Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_OFFN_REG GP_ADC_OFFN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_OFFN

GP_ADC_OFFN : Offset adjust of 'negative' array of ADC-network (effective if 'GP_ADC_SE=0', or 'GP_ADC_SE=1 AND GP_ADC_SIGN=1')
bits : 0 - 9 (10 bit)
access : read-write


GP_ADC_CLEAR_INT_REG

General Purpose ADC Clear Interrupt Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_CLEAR_INT_REG GP_ADC_CLEAR_INT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_CLR_INT

GP_ADC_CLR_INT : Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0.
bits : 0 - 15 (16 bit)
access : write-only


GP_ADC_RESULT_REG

General Purpose ADC Result Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_RESULT_REG GP_ADC_RESULT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_ADC_VAL

GP_ADC_VAL : Returns the 10 bits linear value of the last AD conversion.
bits : 0 - 9 (10 bit)
access : read-only


GP_ADC_DELAY_REG

General Purpose ADC Delay Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_DELAY_REG GP_ADC_DELAY_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEL_LDO_EN

DEL_LDO_EN : Defines the delay before the LDO enable (GP_ADC_LDO_EN). Reset value is 0 µs since the LDO enable should be the first thing to be programmed in the sequence of bringing the GP ADC up.
bits : 0 - 7 (8 bit)
access : read-write


GP_ADC_DELAY2_REG

General Purpose ADC Second Delay Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_ADC_DELAY2_REG GP_ADC_DELAY2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEL_ADC_EN DEL_ADC_START

DEL_ADC_EN : Defines the delay for the GP_ADC_EN bit. Reset value is 16 µs which is the recommended value to wait after enabling the LDO. This is the second step in bringing up the GP ADC.
bits : 0 - 7 (8 bit)
access : read-write

DEL_ADC_START : Defines the delay for the GP_ADC_START bit. Reset value is 17 µs which is the recommended value to wait before starting the GP ADC. This is the third and last step of bringing up the GP ADC
bits : 8 - 23 (16 bit)
access : read-write



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