\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Chip identification register 1.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_ID1 : First character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Chip identification register 2.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_ID2 : Second character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Chip identification register 3.
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_ID3 : Third character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Software compatibility register.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_SWC : SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code.
bits : 0 - 3 (4 bit)
access : read-only
Chip revision register.
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REVISION_ID : Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B'
bits : 0 - 7 (8 bit)
access : read-only
Chip configuration register 1.
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_CONFIG1 : First character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Chip configuration register 2.
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_CONFIG2 : Second character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Chip configuration register 3.
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_CONFIG3 : Third character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only
Chip test register 1.
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Chip test register 2.
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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