\n

Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

CHIP_ID1_REG

CHIP_ID2_REG

CHIP_ID3_REG

CHIP_SWC_REG

CHIP_REVISION_REG

CHIP_CONFIG1_REG

CHIP_CONFIG2_REG

CHIP_CONFIG3_REG

CHIP_TEST1_REG

CHIP_TEST2_REG


CHIP_ID1_REG

Chip identification register 1.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID1_REG CHIP_ID1_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_ID1

CHIP_ID1 : First character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_ID2_REG

Chip identification register 2.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID2_REG CHIP_ID2_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_ID2

CHIP_ID2 : Second character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_ID3_REG

Chip identification register 3.
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID3_REG CHIP_ID3_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_ID3

CHIP_ID3 : Third character of device type '580' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_SWC_REG

Software compatibility register.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_SWC_REG CHIP_SWC_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_SWC

CHIP_SWC : SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code.
bits : 0 - 3 (4 bit)
access : read-only


CHIP_REVISION_REG

Chip revision register.
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_REVISION_REG CHIP_REVISION_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REVISION_ID

REVISION_ID : Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B'
bits : 0 - 7 (8 bit)
access : read-only


CHIP_CONFIG1_REG

Chip configuration register 1.
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_CONFIG1_REG CHIP_CONFIG1_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_CONFIG1

CHIP_CONFIG1 : First character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_CONFIG2_REG

Chip configuration register 2.
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_CONFIG2_REG CHIP_CONFIG2_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_CONFIG2

CHIP_CONFIG2 : Second character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_CONFIG3_REG

Chip configuration register 3.
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_CONFIG3_REG CHIP_CONFIG3_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHIP_CONFIG3

CHIP_CONFIG3 : Third character of Chip Configuration '0M2' in ASCII.
bits : 0 - 7 (8 bit)
access : read-only


CHIP_TEST1_REG

Chip test register 1.
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_TEST1_REG CHIP_TEST1_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CHIP_TEST2_REG

Chip test register 2.
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_TEST2_REG CHIP_TEST2_REG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.