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address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection :
HCLK, PCLK, divider and clock gates
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_DIV : AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 0 - 1 (2 bit)
access : read-write
PCLK_DIV : APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 4 - 9 (6 bit)
access : read-write
OTP_ENABLE : Clock enable for OTP controller
bits : 7 - 14 (8 bit)
access : read-write
Power Management Unit control register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET_ON_WAKEUP : Perform a Hardware Reset after waking up. Booter will be started.
bits : 0 - 0 (1 bit)
access : read-write
PERIPH_SLEEP : Put all peripherals (I2C, UART, SPI, ADC) in powerdown
bits : 1 - 2 (2 bit)
access : read-write
RADIO_SLEEP : Put the digital part of the radio in powerdown
bits : 2 - 4 (3 bit)
access : read-write
OTP_COPY_DIV : Sets the HCLK division during OTP mirroring
bits : 4 - 9 (6 bit)
access : read-write
FORCE_BUCK : Force the DCDC into buck mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed.
bits : 6 - 12 (7 bit)
access : read-write
FORCE_BOOST : Force the DCDC into boost mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed.
bits : 7 - 14 (8 bit)
access : read-write
RETENTION_MODE : Select the retainability of the 4 retention RAM macros. '1' is retainable, '0' is power gated. (3) is RETRAM4 (2) is RETRAM3 (1) is RETRAM2 (0) is RETRAM1
bits : 8 - 19 (12 bit)
access : read-write
System Control register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REMAP_ADR0 : Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: SysRAM 0x3: RetRAM
bits : 0 - 1 (2 bit)
access : read-write
RET_SYSRAM : Sets the development phase mode. If this bit is set, the SysRAM cell will not power gated during sleep (extended sleep). No copy action to SysRAM is done when the system wakes up. For emulating startup time, the OTP_COPY bit still needs to be set.
bits : 2 - 4 (3 bit)
access : read-write
CLK32_SOURCE : Sets the clock source of the 32 kHz clock 0 = RC-oscillator 1 = 32 kHz crystal oscillator
bits : 3 - 6 (4 bit)
access : read-write
OTP_COPY : Enables OTP to SysRAM copy action after waking up PD_SYS
bits : 4 - 8 (5 bit)
access : read-write
PAD_LATCH_EN : Latches the control signals of the pads for state retention in powerdown mode. 0: Control signals are retained 1: Latch is transparant, pad can be recontrolled
bits : 5 - 10 (6 bit)
access : read-write
OTPC_RESET_REQ : Reset request for the OTP controller.
bits : 6 - 12 (7 bit)
access : read-write
DEBUGGER_ENABLE : Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports.
bits : 7 - 14 (8 bit)
access : read-write
TIMEOUT_DISABLE : Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG.
bits : 9 - 18 (10 bit)
access : read-write
SW_RESET : Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ...
bits : 15 - 30 (16 bit)
access : write-only
System status register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAD_IS_DOWN : Indicates that PD_RAD is in power down
bits : 0 - 0 (1 bit)
access : read-only
RAD_IS_UP : Indicates that PD_RAD is functional
bits : 1 - 2 (2 bit)
access : read-only
PER_IS_DOWN : Indicates that PD_PER is in power down
bits : 2 - 4 (3 bit)
access : read-only
PER_IS_UP : Indicates that PD_PER is functional
bits : 3 - 6 (4 bit)
access : read-only
DBG_IS_DOWN : Indicates that PD_DBG is in power down
bits : 4 - 8 (5 bit)
access : read-only
DBG_IS_UP : Indicates that PD_DBG is functional
bits : 5 - 10 (6 bit)
access : read-only
XTAL16_TRIM_READY : Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG.
bits : 6 - 12 (7 bit)
access : read-only
XTAL16_SETTLED : Indicates that XTAL16 has had > 2 ms of settle time
bits : 7 - 14 (8 bit)
access : read-only
Control trimming of the XTAL16M
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTLE_TIME : Defines the delay between applying CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of 250 us. 0x0: XTAL16_SETTLED is set direcly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc.
bits : 0 - 3 (4 bit)
access : read-write
TRIM_TIME : Defines the delay between XTAL16M enable and applying the CLK_FREQ_TRIM_REG in steps of 250 us. 0x0: apply directly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc.
bits : 4 - 11 (8 bit)
access : read-write
Xtal frequency trimming register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINE_ADJ : Xtal frequency fine trimming register. 0x00: lowest frequency 0xFF: highest frequency
bits : 0 - 7 (8 bit)
access : read-write
COARSE_ADJ : Xtal frequency course trimming register. 0x0: lowest frequency 0x7: highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200 us to allow the adjustment to settle.
bits : 8 - 18 (11 bit)
access : read-write
32 kHz oscillator register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL32K_ENABLE : Enables the 32 kHz XTAL oscillator
bits : 0 - 0 (1 bit)
access : read-write
XTAL32K_RBIAS : Setting for the bias resistor of the 32 kHz XTAL oscillator. 0x0: maximum 0x3: minimum Prefered setting will be provided by Dialog.
bits : 1 - 3 (3 bit)
access : read-write
XTAL32K_CUR : Bias current for the 32kHz XTAL oscillator. 0x0: minimum 0x3: default 0xF: maximum For each application there is an optimal setting for which the startup behaviour is optimal.
bits : 3 - 9 (7 bit)
access : read-write
RC32K_ENABLE : Enables the 32 kHz RC oscillator
bits : 7 - 14 (8 bit)
access : read-write
RC32K_TRIM : Controls the frequency of the RC32K oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency
bits : 8 - 19 (12 bit)
access : read-write
XTAL32K_DISABLE_AMPREG : Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock applied at XTAL32Kp. Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km.
bits : 12 - 24 (13 bit)
access : read-write
16 MHz RC-oscillator register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC16M_ENABLE : Enables the 16 MHz RC oscillator
bits : 0 - 0 (1 bit)
access : read-write
RC16M_TRIM : Controls the frequency of the RC16M oscillator. 0x0: lowest frequency 0xF: highest frequency
bits : 1 - 5 (5 bit)
access : read-write
XTAL16_CUR_SET : Bias current for the 16 MHz XTAL oscillator. 0x0: minimum 0x7: maximum
bits : 5 - 12 (8 bit)
access : read-write
XTAL16_BIAS_SH_ENABLE : Enables Ibias sample/hold function in 16 MHz crystal oscillator. This bit should be set when the system wake up and reset before entering deep or extended sleep mode.
bits : 8 - 16 (9 bit)
access : read-write
XTAL16_NOISE_FILT_ENABLE : Enables noise flter in 16 MHz crystal oscillator
bits : 9 - 18 (10 bit)
access : read-write
RCX-oscillator control register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCX20K_TRIM : Controls the frequency of the RCX oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency
bits : 0 - 3 (4 bit)
access : read-write
RCX20K_NTC : Temperature control
bits : 4 - 11 (8 bit)
access : read-write
RCX20K_BIAS : Bias control
bits : 8 - 17 (10 bit)
access : read-write
RCX20K_LOWF : Extra low frequency
bits : 10 - 20 (11 bit)
access : read-write
RCX20K_ENABLE : Enable the RCX oscillator
bits : 11 - 22 (12 bit)
access : read-write
RCX20K_SELECT : Selects RCX oscillator. 0 : RC32K oscillator 1: RCX oscillator
bits : 12 - 24 (13 bit)
access : read-write
Bandgap trimming
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGR_TRIM : Trim register for bandgap
bits : 0 - 4 (5 bit)
access : read-write
BGR_ITRIM : Current trimming for bias
bits : 5 - 14 (10 bit)
access : read-write
LDO_RET_TRIM :
bits : 10 - 23 (14 bit)
access : read-write
BGR_LOWPOWER : Test-mode, do not use. It disables the bandgap core (voltages will continue for some time, but will slowely drift away)
bits : 14 - 28 (15 bit)
access : read-write
Status bit of analog (power management) circuits
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBAT1V_AVAILABLE : Indicates that VBAT1V is available.
bits : 0 - 0 (1 bit)
access : read-only
VBAT1V_OK : Indicates that VBAT1V is above threshold.
bits : 1 - 2 (2 bit)
access : read-only
VDCDC_OK : Indicates that VDCDC is above threshold.
bits : 2 - 4 (3 bit)
access : read-only
LDO_OTP_OK : Indicates that LDO_OTP is in regulation
bits : 3 - 6 (4 bit)
access : read-only
LDO_VDD_OK : Indicates that LDO_VDD is in regulation
bits : 4 - 8 (5 bit)
access : read-only
LDO_ANA_OK : Indicates that LDO_ANA is in regulation. This LDO is used for the general-purpose ADC only
bits : 5 - 10 (6 bit)
access : read-only
BOOST_VBAT_OK : Indicates that VBAT is above threshold while in BOOST converter mode.
bits : 6 - 12 (7 bit)
access : read-only
BANDGAP_OK : Indicates that BANDGAP is OK
bits : 7 - 14 (8 bit)
access : read-only
BOOST_SELECTED : Indicates that DCDC is in boost mode
bits : 9 - 18 (10 bit)
access : read-only
(in CRG)
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFIO_TRIM1_CAP : Trim the RFIO input capacitance 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
bits : 0 - 7 (8 bit)
access : read-write
(in CRG)
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_CD_LF : Trim the LNA output capacitance for CN 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
bits : 0 - 5 (6 bit)
access : read-write
LNA_TRIM_CD_HF : Trim the LNA output capacitance for CN > 19 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
bits : 6 - 17 (12 bit)
access : read-write
(in CRG)
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_GM_HI : Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 0 and 1 00: Minimum transconductance 10: Nominal transconductance 1F: Maximal transconductance
bits : 0 - 5 (6 bit)
access : read-write
LNA_TRIM_GM_LO : Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 2 and 3 00: Minimum transconductance 10: Nominal transconductance 1F: Maximal transconductance
bits : 6 - 17 (12 bit)
access : read-write
(in CRG)
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_TRIM_CGS : Trim the LNA gate-source capacitance 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
bits : 0 - 4 (5 bit)
access : read-write
(in CRG)
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI_COMP01 : RSSI compensation value for LNA gain setting 01 relative to 00 '0x0': -4 '0x1': -3 '0x2': -2 '0x3': -1 '0x4': 0 '0x5': 1 '0x6': 2 '0x7': 3 (reset) '0x8': 4 '0x9': 5 '0xA': 6 '0xB': 7 '0xC': 8 '0xD': 9 '0xE': 10 '0xF': 11
bits : 0 - 3 (4 bit)
access : read-write
RSSI_COMP10 : RSSI compensation value for LNA gain setting 10 relative to 00 Coding identical to RSSI_COMP01.
bits : 4 - 11 (8 bit)
access : read-write
RSSI_COMP11 : RSSI compensation value for LNA gain setting 11 relative to 00 Coding identical to RSSI_COMP01.
bits : 8 - 19 (12 bit)
access : read-write
RSSI_COMP00 : RSSI compensation value for LNA gain setting 00 '0x0': -8 '0x1': -7 '0x2': -6 '0x3': -5 '0x4': -4 '0x5': -3 '0x6': -2 '0x7': -1 '0x8': 0 (reset) '0x9': 1 '0xA': 2 '0xB': 3 '0xC': 4 '0xD': 5 '0xE': 6 '0xF': 7
bits : 12 - 27 (16 bit)
access : read-write
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCO_AMPL_SET : Set the desired amplitude of the VCO'0': minimum amplitude '4': default amplitude 'F': maximum amplitude
bits : 0 - 3 (4 bit)
access : read-write
(in CRG)
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOTP_ACTIVE : Enables the SPOTP testmode. Reset by write or PowerOnReset
bits : 0 - 0 (1 bit)
access : read-write
LDO_OTP_WRITE : Bypass LDO and put VBAT directly on OTP_VDDIO
bits : 1 - 2 (2 bit)
access : read-write
Peripheral divider register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_DIV : Division factor for TIMER0 and TIMER2 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 0 - 1 (2 bit)
access : read-write
TMR_ENABLE : Enable TIMER0 and TIMER2 clock
bits : 3 - 6 (4 bit)
access : read-write
WAKEUPCT_ENABLE : Enable Wakeup CaptureTimer clock
bits : 4 - 8 (5 bit)
access : read-write
I2C_ENABLE : Enable I2C clock
bits : 5 - 10 (6 bit)
access : read-write
UART2_ENABLE : Enable UART2 clock
bits : 6 - 12 (7 bit)
access : read-write
UART1_ENABLE : Enable UART1 clock
bits : 7 - 14 (8 bit)
access : read-write
SPI_DIV : Division factor for SPI 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
bits : 8 - 17 (10 bit)
access : read-write
SPI_ENABLE : Enable SPI clock
bits : 11 - 22 (12 bit)
access : read-write
QUAD_ENABLE : Enable the Quadrature clock
bits : 15 - 30 (16 bit)
access : read-write
Radio PLL control register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFCU_DIV : Division factor for RF Control Unit 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency must be exactly 8 MHz.
bits : 0 - 1 (2 bit)
access : read-write
RFCU_ENABLE : Enable the RF control Unit clock
bits : 3 - 6 (4 bit)
access : read-write
BLE_DIV : Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
bits : 4 - 9 (6 bit)
access : read-write
BLE_LP_RESET : Reset for the BLE LP timer
bits : 6 - 12 (7 bit)
access : read-write
BLE_ENABLE : Enable the BLE core clocks
bits : 7 - 14 (8 bit)
access : read-write
Clock control register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_CLK_SEL : Selects the clock source. 0x0: XTAL16M (check the XTAL16_SETTLED and XTAL16_TRIM_READY bits!!) 0x1: RC16M 0x2/0x3: either RC32k or XTAL32k is used
bits : 0 - 1 (2 bit)
access : read-write
XTAL16M_DISABLE : Setting this bit instantaneously disables the 16 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when 'RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_SETTLED or XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source.
bits : 2 - 4 (3 bit)
access : read-write
XTAL16M_SPIKE_FLT_DISABLE : Disable spikefilter in digital clock
bits : 3 - 6 (4 bit)
access : read-write
RUNNING_AT_32K : Indicates that either the RC32k or XTAL32k is being used as clock
bits : 5 - 10 (6 bit)
access : read-only
RUNNING_AT_RC16M : Indicates that the RC16M clock is used as clock
bits : 6 - 12 (7 bit)
access : read-only
RUNNING_AT_XTAL16M : Indicates that the XTAL16M clock is used as clock, and may not be switched off
bits : 7 - 14 (8 bit)
access : read-only
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