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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

P0_DATA_REG

P05_MODE_REG

P06_MODE_REG

P07_MODE_REG

P0_SET_DATA_REG

P1_DATA_REG

P1_SET_DATA_REG

P1_RESET_DATA_REG

P10_MODE_REG

P11_MODE_REG

P12_MODE_REG

P13_MODE_REG

P14_MODE_REG

P15_MODE_REG

P0_RESET_DATA_REG

P2_DATA_REG

P2_SET_DATA_REG

P2_RESET_DATA_REG

P20_MODE_REG

P21_MODE_REG

P22_MODE_REG

P23_MODE_REG

P24_MODE_REG

P25_MODE_REG

P26_MODE_REG

P27_MODE_REG

P28_MODE_REG

P29_MODE_REG

P00_MODE_REG

P01_PADPWR_CTRL_REG

P2_PADPWR_CTRL_REG

P3_PADPWR_CTRL_REG

P01_MODE_REG

P3_DATA_REG

P3_SET_DATA_REG

P3_RESET_DATA_REG

P30_MODE_REG

P31_MODE_REG

P32_MODE_REG

P33_MODE_REG

P34_MODE_REG

P35_MODE_REG

P36_MODE_REG

P37_MODE_REG

P02_MODE_REG

P03_MODE_REG

P04_MODE_REG

TEST_CTRL_REG

TEST_CTRL2_REG

TEST_CTRL3_REG

TEST_CTRL4_REG

TEST_CTRL5_REG

BIST_CTRL_REG

ROMBIST_RESULTL_REG

ROMBIST_RESULTH_REG


P0_DATA_REG

P0 Data input / output register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DATA_REG P0_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_DATA

P0_DATA : Set P0 output register when written Returns the value of P0 port when read
bits : 0 - 7 (8 bit)
access : read-write


P05_MODE_REG

P05 Mode Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P05_MODE_REG P05_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P06_MODE_REG

P06 Mode Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P06_MODE_REG P06_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P07_MODE_REG

P07 Mode Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P07_MODE_REG P07_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P0_SET_DATA_REG

P0 Set port pins register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_SET_DATA_REG P0_SET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_SET

P0_SET : Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : read-write


P1_DATA_REG

P1 Data input / output register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DATA_REG P1_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_DATA

P1_DATA : Set P1 output register when written Returns the value of P1 port when read
bits : 0 - 7 (8 bit)
access : read-write


P1_SET_DATA_REG

P1 Set port pins register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_SET_DATA_REG P1_SET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_SET

P1_SET : Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : read-write


P1_RESET_DATA_REG

P1 Reset port pins register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_RESET_DATA_REG P1_RESET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1_RESET

P1_RESET : Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : read-write


P10_MODE_REG

P10 Mode Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P10_MODE_REG P10_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P11_MODE_REG

P11 Mode Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P11_MODE_REG P11_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P12_MODE_REG

P12 Mode Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P12_MODE_REG P12_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P13_MODE_REG

P13 Mode Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P13_MODE_REG P13_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P14_MODE_REG

P14 Mode Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P14_MODE_REG P14_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P15_MODE_REG

P15 Mode Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P15_MODE_REG P15_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
bits : 8 - 17 (10 bit)
access : read-write


P0_RESET_DATA_REG

P0 Reset port pins register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_RESET_DATA_REG P0_RESET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_RESET

P0_RESET : Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : read-write


P2_DATA_REG

P2 Data input / output register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DATA_REG P2_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_DATA

P2_DATA : Set P2 output register when written Returns the value of P2 port when read
bits : 0 - 9 (10 bit)
access : read-write


P2_SET_DATA_REG

P2 Set port pins register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_SET_DATA_REG P2_SET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_SET

P2_SET : Writing a 1 to P2[y] sets P2[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 9 (10 bit)
access : read-write


P2_RESET_DATA_REG

P2 Reset port pins register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_RESET_DATA_REG P2_RESET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_RESET

P2_RESET : Writing a 1 to P2[y] sets P2[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 9 (10 bit)
access : read-write


P20_MODE_REG

P20 Mode Register
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P20_MODE_REG P20_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P21_MODE_REG

P21 Mode Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P21_MODE_REG P21_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P22_MODE_REG

P22 Mode Register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P22_MODE_REG P22_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P23_MODE_REG

P23 Mode Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P23_MODE_REG P23_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P24_MODE_REG

P24 Mode Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P24_MODE_REG P24_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P25_MODE_REG

P25 Mode Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P25_MODE_REG P25_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P26_MODE_REG

P26 Mode Register
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P26_MODE_REG P26_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P27_MODE_REG

P27 Mode Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P27_MODE_REG P27_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P28_MODE_REG

P28 Mode Register
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P28_MODE_REG P28_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P29_MODE_REG

P29 Mode Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P29_MODE_REG P29_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P00_MODE_REG

P00 Mode Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P00_MODE_REG P00_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P01_PADPWR_CTRL_REG

Ports 0 and 1 Output Power Control Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P01_PADPWR_CTRL_REG P01_PADPWR_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0_OUT_CTRL P1_OUT_CTRL

P0_OUT_CTRL : 1 = P0_x port output is powered by the 1 V rail 0 = P0_x port output is powered by the 3 V rail bit 0 controls the power of P0[0], bit 7 controls the power of P0[7]
bits : 0 - 7 (8 bit)
access : read-write

P1_OUT_CTRL : 1 = P1_x port output is powered by the 1 V rail 0 = P1_x port output is powered by the 3 V rail bit 8 controls the power of P1[0], bit 13 controls the power of P1[5]
bits : 8 - 21 (14 bit)
access : read-write


P2_PADPWR_CTRL_REG

Port 2 Output Power Control Register
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_PADPWR_CTRL_REG P2_PADPWR_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2_OUT_CTRL

P2_OUT_CTRL : 1 = P2_x port output is powered by the 1 V rail 0 = P2_x port output is powered by the 3 V rail bit 0 controls the power of P2[0], bit 9 controls the power of P2[9],
bits : 0 - 9 (10 bit)
access : read-write


P3_PADPWR_CTRL_REG

Port 3 Output Power Control Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_PADPWR_CTRL_REG P3_PADPWR_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_OUT_CTRL

P3_OUT_CTRL : 1 = P3_x port output is powered by the 1 V rail 0 = P3_x port output is powered by the 3 V rail bit 0 controls the power of P3[0], bit 7 controls the power of P3[7],
bits : 0 - 7 (8 bit)
access : read-write


P01_MODE_REG

P01 Mode Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P01_MODE_REG P01_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P3_DATA_REG

P3 Data input / output register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DATA_REG P3_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_DATA

P3_DATA : Set P3 output register when written Returns the value of P3 port when read
bits : 0 - 7 (8 bit)
access : read-write


P3_SET_DATA_REG

P3 Set port pins register
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_SET_DATA_REG P3_SET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_SET

P3_SET : Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : write-only


P3_RESET_DATA_REG

P3 Reset port pins register
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_RESET_DATA_REG P3_RESET_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P3_RESET

P3_RESET : Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 7 (8 bit)
access : write-only


P30_MODE_REG

P30 Mode Register
address_offset : 0x86 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P30_MODE_REG P30_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P31_MODE_REG

P31 Mode Register
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P31_MODE_REG P31_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P32_MODE_REG

P32 Mode Register
address_offset : 0x8A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P32_MODE_REG P32_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P33_MODE_REG

P33 Mode Register
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P33_MODE_REG P33_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P34_MODE_REG

P34 Mode Register
address_offset : 0x8E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P34_MODE_REG P34_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P35_MODE_REG

P35 Mode Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P35_MODE_REG P35_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P36_MODE_REG

P36 Mode Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P36_MODE_REG P36_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P37_MODE_REG

P37 Mode Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P37_MODE_REG P37_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : See P0x_MODE_REG[PID]
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P02_MODE_REG

P02 Mode Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P02_MODE_REG P02_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P03_MODE_REG

P03 Mode Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P03_MODE_REG P03_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


P04_MODE_REG

P04 Mode Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P04_MODE_REG P04_MODE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PUPD

PID : Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
bits : 0 - 4 (5 bit)
access : read-write

PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write


TEST_CTRL_REG


address_offset : 0xF0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL_REG TEST_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHOW_CLOCKS ENABLE_RFPT SHOW_DC_STATE SHOW_DC_COMP XTAL16M_CAP_TEST_EN SHOW_IF_RO PLL_TST_MODE

SHOW_CLOCKS : 0: normal port function 1: P0[5] = XTAL16M_clk P0[6] = XTAL32K_clk P0[7] = RC16M_clk P1[0] = RC32K_clk P1[1] = RC32K_Low_Jitter_clk
bits : 0 - 0 (1 bit)
access : read-write

ENABLE_RFPT : 0: normal port function 1: enable the RF Production Test Unit. Used to store RX ADC samples or PLL TDC samples in SRAM. See RFPT_CTRL_REG, RFPT_ADDR_REG and RFPT_LEN_REG for details.
bits : 1 - 2 (2 bit)
access : read-write

SHOW_DC_STATE : 0: normal port function 1: show signals to debug/evaluate the DCDC converter: P1[3] = ldo_dig_okP1[2] = ldo_otp_ok P1[1] = dcdc_idleP1[0] = dcdc_clk P0[7] = boost_vbat_ok P0[6] = vdcdc_okP0[5:0] = dcdc_test_out[5:0] (5=short, 4=bypass, 3=sw1v, 2=swout, 1=swp, 0=swn)
bits : 2 - 4 (3 bit)
access : read-write

SHOW_DC_COMP : 0: normal port function 1: show signals to evaluate comparators in DCDC converter: P1[3:1] = dyn_sw_n[2:0]P1[0],P0[7:6] = dyn_sw[2:0]P0[5:3] = cont_sw[2:0] P0[2:0] = dcdc_test_out[2:0] (2=swout, 1=swp, 0=swn)
bits : 3 - 6 (4 bit)
access : read-write

XTAL16M_CAP_TEST_EN : 0: Normal Port function. 1: Show xtal16m_cap_test_outoutput P1[2:1] Notes: - The control signal should go to the radio to enable this test mode. - This register should be zero during scan test!
bits : 4 - 8 (5 bit)
access : read-write

SHOW_IF_RO : 0: Normal Port function. 1: Show IF filter Reference Oscillator I and Q signals. P0[0] = iff_ro_out_i P0[1] = iff_ro_out_q
bits : 5 - 10 (6 bit)
access : read-write

PLL_TST_MODE : 0: Normal operation 1: Show the PLL test mode signals: P0[0] = RCLK P0[1] = NCLK P0[2] = CP_UP P0[3] = CP_DOWN Notes: - The control signal should go to the radio to enable this test mode.
bits : 6 - 12 (7 bit)
access : read-write


TEST_CTRL2_REG


address_offset : 0xF2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL2_REG TEST_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANA_TESTMUX_CTRL RF_IN_TESTMUX_CTRL

ANA_TESTMUX_CTRL : Control of analog test bus switches: 0: all switches open 1: only switch 1 closed 2: only switch 2 closed 3: only switch 3 closed 4: only switch 4 closed 5: switches 1 and 2 closed 6: switches 1 and 4 closed 7: switches 2 and 3 closed 8: switches 3 and 4 closed
bits : 0 - 3 (4 bit)
access : read-write

RF_IN_TESTMUX_CTRL : CConnect the RF input testbus to pins
bits : 8 - 17 (10 bit)
access : read-write


TEST_CTRL3_REG


address_offset : 0xF4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL3_REG TEST_CTRL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_TEST_OUT_SEL RF_TEST_OUT_PARAM

RF_TEST_OUT_SEL : Select a radio block to have its testbus connected to P1[1] and P1[2]. See Table 7 for more information. NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses.
bits : 0 - 5 (6 bit)
access : read-write

RF_TEST_OUT_PARAM : Select which test will be enabled on the block selected by the RF output testbus (see
bits : 8 - 23 (16 bit)
access : read-write


TEST_CTRL4_REG


address_offset : 0xF6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL4_REG TEST_CTRL4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF_TEST_IN_SEL RF_TEST_IN_PARAM

RF_TEST_IN_SEL : Select an RF block to have its test input connected to the input testbus at pins P0[0] and P0[3]. NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses.
bits : 0 - 2 (3 bit)
access : read-write

RF_TEST_IN_PARAM : Select which test will be enabled on the block selected by the RF output testbus (see
bits : 8 - 23 (16 bit)
access : read-write


TEST_CTRL5_REG


address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_CTRL5_REG TEST_CTRL5_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEST_VDD TEST_OTP_VDD TEST_OTP_OTA TEST_OTP_VSS TEST_STRUCT DCDC_NSW DCDC_PSW DCDC_OUTSW DCDC_FORCE_IDLE

TEST_VDD : VDD on P1[1], VDD_REF (=ADC) on P1[2]
bits : 0 - 0 (1 bit)
access : read-write

TEST_OTP_VDD : VDD_OTP on P1[2], 1uA bias sink on P1[1]
bits : 1 - 2 (2 bit)
access : read-write

TEST_OTP_OTA : Output of OTA inside LDO-OTP is mapped on P1[2]. This voltage will slowely rise due to capacitor leakage.
bits : 2 - 4 (3 bit)
access : read-write

TEST_OTP_VSS : VSS_OTP (0V) mapped on P1[2]
bits : 3 - 6 (4 bit)
access : read-write

TEST_STRUCT : 4 bits to select which test-structure is mapped on P1[1] 0 : open 1 : VDD (1.2V) 2 : 10uA into 66k = 5/3 x 40k (W/L=0.45/22.33) 3 : 1uA into 700k = 18.5 x 40k (W/L=0.45/22.33) 4 : 1uA(same as going into 700k) 5 : AVS (0V) 6 : 5uA into nMOST (svt) 2x1u/110n 7 : 5uA into nMOST (hvt) 2x1u/110n 8 : 5uA into nMOST (UD18) 2x1u/260n 9 : 5uA into nMOST (OD33) 2x1u/500n a : 7.5uA into nMOST (na25) 4x1u/1.2u b : 5uA into nMOST (0vt) 4x1u/300n c : VDD - 5uA from pMOST (svt) 2x1u/110n d : VDD - 5uA from pMOST (hvt) 2x1u/110n e : VDD - 5uA from pMOST (OD33) 2x1u/400n f : VDD - 5uA from pMOST (UD18) 2x1u/260n
bits : 8 - 19 (12 bit)
access : read-write

DCDC_NSW : Close nMOS switch between 'switch' and 'gnd'
bits : 12 - 24 (13 bit)
access : read-write

DCDC_PSW : Close pMOS switch between 'switch' and 'vbat3v'
bits : 13 - 26 (14 bit)
access : read-write

DCDC_OUTSW : Close pMOS switch between 'switch' and 'vdcdc'
bits : 14 - 28 (15 bit)
access : read-write

DCDC_FORCE_IDLE : Keep the DCDC-converter in the idle state.
bits : 15 - 30 (16 bit)
access : read-write


BIST_CTRL_REG


address_offset : 0xFA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIST_CTRL_REG BIST_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM_BIST_CONFIG ROMBIST_ENABLE RAMBIST_ENABLE SHOW_BIST ROM_BIST_BUSY RETRAM_BIST_LINE_FAIL RETRAM_BIST_FAIL RETRAM_BIST_BUSY SYSRAM_BIST_LINE_FAIL SYSRAM_BIST_FAIL SYSRAM_BIST_BUSY RAM_BIST_PATTERN

RAM_BIST_CONFIG : Bist configuration: 00 = Perform all 8 phases 01 = Perform only phase 1 10 = Perform only phase 3 and 4 11 = Perform only phase 6
bits : 0 - 1 (2 bit)
access : read-write

ROMBIST_ENABLE : Enable the ROM bist
bits : 2 - 4 (3 bit)
access : read-write

RAMBIST_ENABLE : Enable the RAM bists
bits : 3 - 6 (4 bit)
access : read-write

SHOW_BIST : Map bist results on pins: P0[7] = SYSRAM_BIST_BUSY P0[6] = SYSRAM_BIST_FAIL P0[5] = SYSRAM_BIST_LINE_FAIL P0[4] = RETRAM_BIST_BUSY P0[3] = RETRAM_BIST_FAIL P0[2] = RETRAM_BIST_LINE_FAIL P0[1] = ROM_BIST_BUSY
bits : 4 - 8 (5 bit)
access : read-write

ROM_BIST_BUSY : Read version of bist status
bits : 5 - 10 (6 bit)
access : read-only

RETRAM_BIST_LINE_FAIL : Read version of bist status
bits : 6 - 12 (7 bit)
access : read-only

RETRAM_BIST_FAIL : Read version of bist status
bits : 7 - 14 (8 bit)
access : read-only

RETRAM_BIST_BUSY : Read version of bist status
bits : 8 - 16 (9 bit)
access : read-only

SYSRAM_BIST_LINE_FAIL : Read version of bist status
bits : 9 - 18 (10 bit)
access : read-only

SYSRAM_BIST_FAIL : Read version of bist status
bits : 10 - 20 (11 bit)
access : read-only

SYSRAM_BIST_BUSY : Read version of bist status
bits : 11 - 22 (12 bit)
access : read-only

RAM_BIST_PATTERN : Pattern to use for the BIST tests: 00 = Use 0x5555 as test data 01 = Use 0x5A5A as test data 10 = Use 0x0000 as test data 11 = Use 0x0F0F as test data
bits : 12 - 25 (14 bit)
access : read-write


ROMBIST_RESULTL_REG


address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROMBIST_RESULTL_REG ROMBIST_RESULTL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROMBIST_RESULTL

ROMBIST_RESULTL : Read version of bist status, result[15:0]
bits : 0 - 15 (16 bit)
access : read-only


ROMBIST_RESULTH_REG


address_offset : 0xFE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROMBIST_RESULTH_REG ROMBIST_RESULTH_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROMBIST_RESULTH

ROMBIST_RESULTH : Read version of bist status, result[31:16]
bits : 0 - 15 (16 bit)
access : read-only



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